Baudouin Martineau

A 65-nm CMOS Fully Integrated Transceiver Module for 60-GHz Wireless HD Applications

This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

A 60 GHz wideband power amplifier (PA) is fabricated in a standard CMOS SOI 65 nm process. The PA is based on two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high-resistivity SOI substrate (3 kΩ · cm). The PA measurements are carried out for supply voltages VDD going from 1.2 V to 2.6 V and achieve a saturation power of 10 dBm to 16.5 dBm respectively. The peak power-added efficiency (PAE) is higher than 20% for all applied VDD values.

A 53-to-68GHz 18dBm power amplifier with an 8-way combiner in standard 65nm CMOS

CMOS circuits operating up to 60GHz have been demonstrated to satisfy the market demand for high data rates and frequency bandwidths [1–6]. However, 60GHz products need an improvement in power performance as well as transistor reliability for large signal operation. Moreover, Class-A or Class-AB power amplifiers (PA) are mandatory to overcome the difficulty of the limited maximum available gain (MAG) at mm-Wave frequencies [1–6] and the high linearity required by the OFDM modulation used in the IEEE 802.15.3c wireless HD standard. That means a maximum drain-source voltage swing of twice the DC voltage, which introduces specific design or supply voltage in order to respect reliability constraints [1,7]. This paper describes a PA with 8 power-combined ways and cascode topology in a 7-metal-layer 65nm CMOS process which covers the full band for 60GHz wireless applications. The presented circuit operates at a standard supply of 1.2V or 1.8V, and achieves a saturated output power of 16.6dBm and 18.1dBm respectively. The measured output power is high for CMOS while insuring reliability for time-dependent dielectric breakdown (TDDB) and hot-carrier-injection (HCI) degradation.

Design for millimeter-wave applications in silicon technologies

This paper presents the potentialities of advanced BiCMOS and CMOS technologies for millimeter-wave applications. To begin, the target applications in these frequency bands are presented: from automotive cruise control radars to wireless links. Then, a large overview of the technological offer to address these applications is presented: SiGe BiCMOS, nanometer bulk and SOI CMOS technologies. This work focuses both on active and passive devices (BEOL) behavior to suit for design above 20 GHz. The paper continues with a presentation of several solutions for integrated circuits on the presented topic: front-end receiver blocks, transmission blocks and frequency synthesis solutions. An overview of state of the art silicon circuits is given. As a conclusion, perspectives regarding future challenges in terms of system integration and applications are discussed.

1.8 dB insertion loss 200 GHz CPW band pass filter integrated in HR SOI CMOS Technology

Today, measurement of 65 nm CMOS [Dambrine, G., et al., 2005] and 130 nm-based SiGe HBTs [Chevalier, p. et al., 2004] technologies demonstrate both fT (current gain cut-off frequency) and fmax (maximum oscillation frequency) higher than 200 GHz, which are clearly comparable to advanced commercially available 100nm III-V HEMT. This increase allows new millimeter wave (MMW) applications on silicon. One of the success keys is then the passive integration. In this paper, on-chip coplanar waveguides (CPWs), which have been achieved in STMicroelectronics advanced nanometric RF CMOS High Resistivity (HR) SOI (rho > 1 kOmegaldrcm) process, and characterized up to 220 GHz are reported. Moreover, for the first time passive circuits working @ 220 GHz have been achieved and characterized demonstrating state-of-the-art performances and good agreement with electric simulations using developed models.

94GHz power-combining power amplifier with +13dBm saturated output power in 65nm CMOS

A power combining power amplifier utilizing cascode topology and transformer-based matching elements is presented in this paper. The amplifier achieves +13 dBm saturated output power at 94 GHz with a standard 1.2 V supply and occupies an active area of only 0.069 mm2. Amplifier is implemented in an industrial 65nm CMOS process taking into account reliability issues at high output power level. The amplifier is also ESD-protected at the input and at the output.

A 60GHz power amplifier with 14.5dBm saturation power and 25% peak PAE in CMOS 65nm SOI

A 60GHz wideband power amplifier (PA) is fabricated in standard CMOS SOI 65nm process. The PA is constituted by two cascode stages. Input, output and inter-stage matching use coplanar wave guide (CPW) transmission lines that have low losses thanks to the high resistivity SOI substrate. The PA measurements are carried out for supply voltages VDD going from 1.2V to 2.6V and achieve a saturation power of 10dBm to 16.5dBm respectively. The peak power added efficiency is higher than 20% for all applied VDD values.

2.10 A 60GHz 28nm UTBB FD-SOI CMOS reconfigurable power amplifier with 21% PAE, 18.2dBm P 1dB and 74mW P DC

The widespread deployment of high-data-rate wireless connectivity was enabled by the adoption of the WiGig (802.11ad) standard, consequently placing a challenge on integrated Power Amplifiers (PAs). To comply with system requirements, the PA must cover bands from 57 to 66GHz and deliver up to 10dBm RF modulated power, while OFDM modulations up to 16 or 64QAM are supported, implying a large Peak-to-Average Power Ratio (PAPR).

80 GHz low noise amplifiers in 65nm CMOS SOI

A 1 stage and 3 stages 80 GHz low noise amplifiers (LNA) are presented in this paper. Both mm-wave LNA are integrated in a 65 nm CMOS SOI process. The one stage amplifier exhibits 2.1 dB gain and a noise figure of 4.5 dB at 80 GHz. The input and output return losses are -13 dB and -6 dB respectively. This amplifier consumes 22 mW from a supply voltage of 1.2 V and occupies an area of 0.64 mm2 including the pads. The 3 stages LNA presents a gain of 7.2 dB and a noise figure of 5.7 dB at 80 GHz with an input and output matching better than -14 dB and -10 dB respectively. The 3 stages amplifier consumes 70 mW from a supply voltage of 1V and occupies an area of 0.98 mm2 including pads.

A 56GHz LC-tank VCO with 17% tuning range in 65nm bulk CMOS for wireless HDMI applications

A voltage controlled oscillator (VCO) with 56GHz central frequency and 17% tuning range is presented. The oscillation frequency is tuned both by an analog input and a three-bit digital control bus using the same type of differential varactors. It achieves a record FOMT (considering tuning range) of 186.8 dBc/Hz and it is able to address the full wireless HDMI band. The VCO is implemented in a 65nm bulk CMOS process and dissipates 15 mW from a 1.2 V supply.