Nathalie Deltimple

A reconfigurable RF power amplifier biasing scheme

A reconfigurable power amplifier (PA) is studied in this paper, dedicated to multi-mode, multi-standard radio frequency front-end (RFFE), from a low cost approach. The reconfigurable amplifier topology is presented, made up of two-stages independently controllable by the biasing scheme proposed which allows the dynamic modification of the quiescent current of the RF transistor, to adapt both its linearity and its output power in order to fulfill different standards specifications.

Doherty amplifier optimization using robust genetic algorithm and Unscented Transform

A robust genetic circuit optimizer using Unscented Transform and Non-dominated Sorting Genetic Algorithm-II is presented. The algorithm provides significant computational cost reduction compared to Monte Carlo method. The Unscented Transform permits circuit performance uncertainties determination from components uncertainties, thus, a search through robustness can be approached. Besides reduced computational effort, a plethora of possibilities offered to circuit designer by the multi-objective search can be observed as result. Doherty power amplifier was used as case study.

Linearization of a 65nm CMOS power amplifier with a Cartesian Feedback for W-CDMA standard

A study based on improving linearity of an integrated RF power amplifier (PA) has been done for W-CDMA standard. This power amplifier had been designed in 65nm CMOS of STMicroelectronics under Cadence. The chosen linearization technique is a Cartesian Feedback (CFB). Thanks to this linearization technique, the ACPR has been improved by 22dB at 5MHz from the carrier for an output power of 18dBm.

Design of Class-E power VCO in 65nm CMOS technology: Application to RF transmitter architecture

This paper investigates the feasibility of designing a RF TX architecture based on a Power VCO, operating at 1.95 GHz for UMTS/WCDMA standard. The Power VCO uses 2.5 V supply voltage and is designed using 65 nm CMOS technology from ST Microelectronics. The Power VCO is made up of an oscillating Power Amplifier (PA). In order to fulfil UMTS/W-CDMA requirements, especially on output power with regards to efficiency to save battery life, the used PA is a two-stage Class E PA. The output 1 dB compression point (CP1) is 22 dBm and Power Added Efficiency (PAE) @CP1 is 55.1%. This PA is then included in a loop to realize oscillation condition. The Power VCO oscillates @ 1.95 GHz, achieves an output power of 23.3 dBm with 60.3% PAE.

A SiGe controlled-class power amplifier applied to reconfigurable mobile systems

An integrated two-stage reconfigurable power amplifier (PA) operating at 1.75 GHz for GSM1800 (DCS) and 1.95 GHz for UMTS/WCDMA is proposed. The PA uses 2.5 V supply voltage and was designed using 0.25 fun SiGe BiCMOS technology from ST Microelectronics. In order to fulfill both DCS and UMTS/W-CDMA requirements, especially on efficiency and linearity respectively, the amplifier is able to shift its two-stage classes of operation independently, by acting on bias circuits and tuning output network. To fulfill UMTS linearity requirement, PA operates in class A/AB mode with 27% PAE at the required 24 dBm output power whereas to fulfill DCS output power and efficiency requirements, PA operates in class AB/F mode with 49% PAE at the required 27 dBm output power and a maximum of 70% PAE is reached.

Design of a mixed-signal Cartesian Feedback loop for a low power zero-IF WCDMA transmitter

In this paper, an improved digital-stage design of a mixed-signal Cartesian Feedback loop for a zero-IF WCDMA transmitter is presented. The transmitter architecture consists of an analog stage including filters, I/Q modulator, feedback I/Q demodulator and a digital stage which adjusts the phase misalignment around the loop. We propose an optimized CORDIC design for the digital part in order to improve the system operating frequency without increasing the silicon surface area. ASIC synthesis proves that using a not fully pipelined CORDIC architecture allows us to reach 230 MHz with system power consumption under 4.3 mw which is two times less than a fully analog system.

A 27.5-dBm linear reconfigurable CMOS power amplifier for 3GPP LTE applications

In this paper, a reconfigurable power amplifier (PA) fully integrated in 65-nm CMOS technology, combining Envelope Tracking (ET) and Power Transistor Switching (PTS) techniques, and robust to battery depletion is presented. The main objective of the proposed architecture is to significantly improve the average efficiency in comparison with a stand-alone power amplifier at power back-off. A distributed active transformer (DAT) is also implemented to recombine power generated by the parallelized power cells which can be turned on/off in response to the desired output power. Simulations were conducted in the 3GPP LTE band at 2.535GHz to validate the proposed implementation. Results show that the proposed topology provides higher power added efficiency (PAE) and reduced current consumption at power back-off compared to a stand-alone PA. The most significant improvement is obtained at 9 dB back-off from 27.5dBm where PAE is improved by 8%.

A programmable CMOS RF frequency synthesizer for multi-standard wireless applications

This paper deals with a new frequency synthesizer dedicated to multi-standard wireless applications. It converts a 50 MHz wave clock into two outputs in quadrature phase. It takes advantage of the DLL topology in terms of jitter and phase noise and has no external element. Simulations of the structure designed with a 130 nm SOI CMOS technology confirming the performance of the system are also presented.

A Broadband 4.5–15.5-GHz SiGe Power Amplifier With 25.5-dBm Peak Saturated Output Power and 28.7% Maximum PAE

This paper presents the design of a broadband power amplifier (PA) in 130-nm SiGe BiCMOS technology. First, a single-stage broadband single-cell PA covering the 4.5-18-GHz frequency band is introduced. In this frequency range, this single cell achieves a measured gain, saturated output power ( Psat), output 1-dB compression point ( P1dB), and power-added efficiency (PAE) in the range from 12.8 to 15.7 dB, 18.8 to 23.7 dBm, 16.7 to 19.5 dBm, and 11.4 to 31.9%, respectively. Its peak saturated output power and maximum PAE are both obtained at 8.5 GHz. Second, to increase the output power, a PA consisting of two parallel broadband cells with a power combination is presented. This PA operates in the 4.5-15.5-GHz frequency range with measured gain, Psat, P1dB, and PAE in the range from 11 to 16.6 dB, 21.3 to 25.5 dBm, 18.7 to 21.7 dBm, and 11.9 to 28.7%, respectively. It achieves its peak saturated output power of 25.5 dBm at 8.5 GHz and its maximum PAE of 28.7% with an associated output power of 23.6 dBm at 6.5 GHz. Each of those two PAs achieves better performances than the state-of-the-art in broadband SiGe technology when comparing the output power level and efficiency.

Interacting Multiple Model Based Detector to Compensate Power Amplifier Distortions in Cognitive Radio

For a battery driven terminal, the power amplifier (PA) efficiency must be optimized. Consequently, non-linearities may appear at the PA output in the transmission chain. To compensate these distortions, one solution consists of using a digital detector based on a Volterra model of both the PA and the channel and a Kalman filter (KF) based algorithm to jointly estimate the Volterra kernels and the transmitted symbols. Here, we suggest addressing this issue when dealing with cognitive radio (CR). In this case, additional constraints must be taken into account. Since the CR terminal may switch from one sub-band to another, the PA non-linearities may vary over time. Therefore, we propose to design a digital detector based on an interacting multiple model combining various KF based estimators using different model parameter dynamics. This makes it possible to track the time variations of the Volterra kernels while keeping accurate estimates when those parameters are static. Furthermore, the single and multicarrier cases are addressed and validated by simulation results. Our solution corresponds to a compromise between computational cost and bit-error-rate performance.