Behrooz Parhami

Fault-Tolerant Reversible Circuits

Reversible hardware computation, that is, performing logic signal transformations in a way that allows the original input signals to be recovered from the produced outputs, is helpful in diverse areas such as quantum computing, low-power design, nanotechnology, optical information processing, and bioinformatics. We propose a paradigm for performing such reversible computations in a manner that renders a wide class of circuit faults readily detectable at the circuits outputs. More specifically, we introduce a class of reversible logic gates (consisting of the well-known Fredkin gate and a newly defined Feynman double-gate) for which the parity of the outputs matches that of the inputs. Such parity-preserving reversible gates, when used with an arbitrary synthesis strategy for reversible logic circuits, allow any fault that affects no more than a single logic signal to be detectable at the circuits primary outputs. We show the applicability of our design strategy by demonstrating how the well-known, and very useful, Toffoli gate can be synthesized from parity- preserving gates and apply the results to the design of a binary full-adder circuit, which is a versatile and widely used element in digital arithmetic processing.

Generalized signed-digit number systems: a unifying framework for redundant number representations

Signed-digit (SD) number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha , . . ., -1, 0, 1, . . ., alpha ), where alpha is an arbitrary integer in the range 1/2r >

Carry-free addition of recoded binary signed-digit numbers

Signed-digital number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha ,...,-1,0,1,..., alpha ), where alpha is an arbitrary integer in the range r/2 >

AUTOMATIC RECOGNITION OF PRINTED FARSI TEXTS

Abstract The automatic recognition of printed Farsi (Persian) texts is complicated by several properties of the Farsi script: (a) connectivity of symbols, (b) similarity of groups of symbols, (c) highly variable widths, (d) subword overlap, and (e) line overlap. In this paper, a technique for the automatic recognition of printed Farsi texts is presented and its steps are discussed as follows: (1) digitization, (2) editing, (3) line separation, (4) subword separation, (5) symbol separation, (6) recognition, and (7) postprocessing. The most notable contributions of this work are in algorithms for steps (5) and (6) above. Practical application of the technique to Farsi newspaper headlines has been 100% successful. However, smaller type fonts, which could not be handled by the coarse digitization hardware used, will no doubt result in less than perfect recognition. The technique is also applicable with little or no modification to printed Arabic and Urdu texts which use the same alphabet as Farsi.

Associative memories and processors: An overview and selected bibliography

A survey of associative processing, techniques is presented, together with a guide to the published literature in this field. Some familiarity with the basic concepts of associative-processing is assumed. The references have been divided into four groups dealing with architectural concepts, hardware implementation, software considerations, and application areas. The discussion of architectural concepts consists of a classification of associative devices into four major categories (fully parallel, bit-serial, word-serial, and block-oriented) and an enumeration of techniques for dealing with multiple responses and hardware faults. With respect to hardware implementation, considerations are given to the basic operations implemented, hardware elements used (e.g., cryoelectrics, magnetic elements, and semiconductors), and physical characteristics such as speed, size, and cost. The discussion of software aspects of associative devices deals with synthesis of algorithms, programming problems, and software simulation. The application areas discussed include solution of some mathematical systems, radar signal processing, information storage and retrieval, and performance of certain control functions in computer systems.

A unified formulation of honeycomb and diamond networks

Honeycomb and diamond networks have been proposed as alternatives to mesh and torus architectures for parallel processing. When wraparound links are included in honeycomb and diamond networks, the resulting structures can be viewed as having been derived via a systematic pruning scheme applied to the links of 2D and 3D tori, respectively. The removal of links, which is performed along a diagonal pruning direction, preserves the networks node-symmetry and diameter, while reducing its implementation complexity and VLSI layout area. In this paper, we prove that honeycomb and diamond networks are special subgraphs of complete 2D and 3D tori, respectively, and show this viewpoint to hold important implications for their physical layouts and routing schemes. Because pruning reduces the node degree without increasing the network diameter, the pruned networks have an advantage when the degree-diameter product is used as a figure of merit. Additionally, if the reduced node degree is used as an opportunity to increase the link bandwidths to equalize the costs of pruned and unpruned networks, a gain in communication performance may result.

A highly parallel computing system for information retrieval

The tremendous expansion in the volume of recorded knowledge and the desirability of more sophisticated retrieval techniques have resulted in a need for automated information retrieval systems. However, the high cost, in programming and running time, implied by such systems has prevented their widespread use. This high cost stems from a mismatch between the problem to be solved and the conventional architecture of digital computers, optimized for performing serial operations on fixed-size arrays of data.

Cayley graphs as models of deterministic small-world networks

Many real networks, including those in social, technological, and biological realms, are small-world networks. The two distinguishing characteristics of small-world networks are high local clustering and small average internode distance. A great deal of previous research on small-world networks has been based on probabilistic methods, with a rather small number of researchers advocating deterministic models. In this paper, we further the study of deterministic small-world networks and show that Cayley graphs may be good models for such networks. Small-world networks based on Cayley graphs possess simple structures and significant adaptability. The Cayley-graph model has pedagogical value and can also be used for designing and analyzing communication and the other real networks.

Configurable arithmetic arrays with data-driven control

Configurable digital systems offer flexibility that leads to cost reduction, performance tuning, and fault tolerance. While one can use FPGA-based methods to synthesize configurable arithmetic structures, this approach results in limited functionality and/or excessive complexity, given that off-the-shelf FPGAs are endowed with only bit-level computational capabilities. Using serial arithmetic cells can increase the ratio of resources devoted to computation (arithmetic, logic) versus communication (wiring), thereby improving per-chip performance or cost-effectiveness. When combined with pipelining, even the absolute latency can be improved. We argue that a controlled-precision digit-serial additive multiplier constitutes an ideal building block for configurable arithmetic arrays and detail our solutions for control of functionality, selection of precision, and reduction of power dissipation within such an array.

On the implementation of arithmetic support functions for generalized signed-digit number systems

Ordinary signed-digit (OSD) number representation systems have been defined for any radix r>or=3 with digit values ranging over the set (- alpha . . .,-1,0,1. . ., alpha ), where alpha is an arbitrary integer in the range r/2 0 and beta >0) explicitly. Zero detection, sign detection, and overflow handling are also treated in depth. >