Behrouz Nowrouzian

Optimization of FIR digital filters over the canonical signed-digit coefficient space using genetic algorithms

In a recent paper a novel approach was presented for the restoration of canonical signed-digit (CSD) numbers to their correct format after the application of crossover and mutation operations in genetic algorithms. This paper is concerned with the development of a new technique for the optimization of FIR digital filters over the CSD coefficient space based on genetic algorithms. This optimization technique exploits the aforementioned restoration of CSD numbers in conjunction with the conventional crossover and mutation operators in addition to a new local mutation operator. The resulting technique is applicable not only to the global optimization of FIR digital filters, but also the conversion of digital filters with specified infinite-precision coefficients to their corresponding finite precision CSD coefficients. An application example is given to illustrate the resulting technique.

A novel modified branch-and-bound technique for discrete optimization over canonical signed-digit number space

A novel algorithm is presented for the design of DSP systems by optimization using the branch-and-bound technique over the canonical signed-digit (CSD) multiplier coefficient space. The proposed algorithm has two main salient features: (1) For a given infinite-precision decimal floating radix-point multiplier coefficient x, it can directly provide the corresponding decimal floating radix-point values for the smallest representable CSD coefficient greater than x and the largest representable CSD coefficient less than x, where these CSD coefficients have pre-specified wordlength and number of nonzero digits. (2) It does not make any recourse to conversion from CSD to decimal, and vice versa, from decimal to CSD conversion. The proposed algorithm finds applications in the optimization of multi-rate IIR or FIR digital filters over the CSD coefficient space.

Optimization of FRM FIR Digital Filters Over CSD and CDBNS Multiplier Coefficient Spaces Employing a Novel Genetic Algorithm

It is well known that frequency response masking (FRM) FIR digital filters can be designed to exhibit very sharp-transition bands at the cost of slightly larger filter lengths as compared to the conventional FIR digital filters. The FRM FIR digital filters permit efficient hardware implementations due to an inherently large number of zerovalued multiplier coefficients in their transfer functions. The hardware complexity of these FIR digital filters can be further reduced by employing computationally efficient number systems for the representation of the constituent non-zero-valued multiplier coefficients. This paper presents a novel genetic algorithm for the design and discrete optimization of FRM FIR digital filters over the conventional canonical signed-digit (CSD) as well as the emerging double base number system (DBNS) multiplier coefficient spaces. This genetic algorithm is based on a pair of indexed look-up tables (LUTs) of permissible CSD/DBNS numbers whose indices form a closed set under the genetic algorithm operations of crossover and mutation. The CSD/DBNS values themselves permit pre-specified word-lengths and pre-specified number of non-zero bits. The salient feature of the proposed genetic algorithm is that it automatically leads to legitimate CSD/DBNS multiplier coefficients without any recourse to gene repair during optimization. The main features of the proposed genetic algorithm are demonstrated through its application to the design of a pair of low-pass and band-pass FRM FIR digital filters.

A Diversity Controlled Genetic Algorithm for Optimization of FRM Digital Filters over DBNS Multiplier Coefficient Space

This paper presents a novel diversity controlled (DC) genetic algorithm (GA) for the optimization of frequency-response masking (FRM) FIR digital filters over the double base number system (DBNS) multiplier coefficient space. The use of DBNS multiplier coefficients reduces the complexity and power consumption in the hardware implementation of the resulting FRM FIR digital filters. A direct application of GAs to the design of FRM FIR digital filters may result in chromosomes which do not conform to the DBNS format due to the underlying crossover and mutation operations. The proposed algorithm uses a DBNS based indexed look-up table (LUT) to ensure generation of valid DBNS multiplier coefficients through out the course of genetic optimization. An application example is given for the design of an FRM FIR lowpass digital filter. The resulting FIR digital filter outperforms a corresponding infinite-precision digital filter obtained by using the Parks-McClellan technique.

Crossover and mutation in genetic algorithms employing canonical signed-digit number system

In this paper, a novel approach is presented for the restoration of canonical signed-digit (CSD) numbers to their correct format after the application of crossover and mutation operations in genetic algorithms. The proposed approach has two main distinct features: First, it employs the same restoration process for both crossover and mutation operations, yielding the process as uniform. Second, it is based on a local, as opposed to global, restoration of the produced offspring numbers, making the corresponding computational implementation efficient. A new technique is also proposed to predict the illegal break-points for the crossover and the illegal bit-locations for the mutation operation, preventing the possibility of generating any out-of-range CSD numbers. An application example is given to illustrate the results.

A comprehensive approach to the design of digit-serial modified booth multipliers

Presents a novel approach to the design and gate-level implementation of digit-serial modified Booth multipliers. The proposed approach is based on the decomposition of the multiplicand and the multiplier each into a unique set of D radix-2/sup D/ components, where D represents the digit-size being used. This permits the desired final product to be formed in terms of the decomposed components of the multiplicand and the multiplier. Empirical results are presented to show the efficiency of the resulting implementations using Actel 1.2 /spl mu/ FPGA technology, where the efficiency is quantified by the throughput per unit area. It is shown that the maximum efficiency is achieved by using digit-serial multipliers operating between the full bit-serial and the full bit-parallel mode.<<ETX>>

Design and implementation of an area and time efficient systolic parallel Booth multiplier

This paper presents combined area-efficient and time-efficient systolic architectures for parallel Booth multiplication. These systolic architectures employ composite (instead of fine grained) cells in order to optimize the silicon area and latency. The complexity of the composite cell is controllable by choosing the proper input size. The composite cell design takes advantages of algorithmic improvements within the cell. These cells are connected only to the neighbors.<<ETX>>

Stability analysis of multiple-feedback oversampled /spl Sigma/-/spl Delta/ A/D converter configurations

This paper is concerned with the estimation of the maximum DC input signal level for five different practical feedforward and multiple-feedback oversampled /spl Sigma/-/spl Delta/ A/D converters. This technique is based on replacing the constituent quantizer by a uniformly distributed additive white noise source and a variable gain element, assuming the following conditions are satisfied: a) the quantizer input signal and quantization error are uncorrelated, b) the quantizer input signal is Gaussian distributed, and c) the quantization noise is white. It is shown that the statistical estimation technique is quite accurate for /spl Sigma/-/spl Delta/ A/D converters with small noise power gains, but that the accuracy tends to decrease for A/D converters having larger noise power gains. It is further shown that this reduction in accuracy stems from the fact that the assumptions listed under a), b), and c) are not exactly satisfied. It is finally shown that the probability density function of the input signal to the quantizer may be modelled more accurately using the Gram-Charlier series.

A new approach to the exact design of LDI lattice digital filters

This paper presents a new approach to the exact design and synthesis of lossless discrete-integrator (LDI) lattice digital filters. The proposed approach is based on a discrete-time prototype reference filter which consists of a symmetrical lattice two-port network inserted between equal resistive source and load terminations, where the constituent lattice two-port network consists of LDI reactances as its canonical impedances. The salient feature of this prototype reference filter is that it permits the main important steps in the lattice digital filter synthesis to be performed directly in the discrete-time z-domain in terms of the LDI monomial. An example is given to illustrate the application of the proposed method to the design of an LDI lattice digital filter having a third-order elliptic lowpass magnitude-frequency characteristic.<<ETX>>

A novel technique to estimate the statistical properties of /spl Sigma/-/spl Delta/ A/D converters for the investigation of DC stability

Concerns the development of a novel technique for the determination of the moments of the quantizer input signal for /spl Sigma/-/spl Delta/ A/D converters. The starting point in this technique is the characterization of the quantizer output signal bit pattern. In the case of first-order /spl Sigma/-/spl Delta/ A/D converters this is facilitated by exploiting the fact that the spectrum of this bit pattern contains a dominant tone indicating that the bit pattern is almost periodic. In the case of higher-order A/D converters, this is achieved by taking into account that in stable /spl Sigma/-/spl Delta/ A/D converters, the constituent quantizer almost always operates in its overload-free region. Then, the quantizer input signal can be determined in terms of the DC input signal and in terms of the estimated quantizer output signal bit pattern. The desired quantizer input signal moments can then be obtained in a straightforward fashion. An application example is given to illustrate the accuracy of the proposed moment estimation technique.