Edith Kussener

A resistor-free temperature-compensated CMOS current reference

This paper presents a resistor-free temperature compensated CMOS current reference designed in a standard 0.18 um CMOS process. The temperature compensation scheme is achieved by combining a PTC (Positive Temperature Coefficient) current generator circuit with a NTC (Negative Temperature Coefficient) current generator circuit. The proposed design is shown to be less sensitive to process and temperature variations and well suited for integration into other circuits as an accurate and stable current source. Simulation results for the proposed current reference show a temperature coefficient of 170 ppm/°C over a temperature range of 20 °C to 120 °C and an output current variation of 3% over a power supply range of 2 V to 3 V.

On-Chip Voltage Regulator Protecting Against Power Analysis Attacks

The on-chip voltage regulator proposed in this paper has been specifically developed for smart cards. Its purpose is to protect the supplied system against power analysis attacks. It allows to generate the internal power supply voltage from the external power supply voltage provided by card readers, while ensuring the uncorrelation between the external power supply current and the internal power supply current. The power supply current of an electronic system can be decomposed into a DC component, which contains little information, and an AC component, which handles considerably more. In order to reach a good compromise between regulation and security, while respecting the smart card stringent technological constraints, these two components are treated separately by a bi-channel power structure. The presented implementation has been simulated from the process parameters of a STMicroelectronics 0.18 mum CMOS technology. It allows to generate a 1.8 V output voltage from a 2 to 5.5 V input voltage range. The structure has been sized to handle a 25 mA DC current while hiding a 20 MHz AC current presenting 75 mA peaks. Its estimated area is approximatively 0.8 mm2.

High speed voltage follower for standard BiCMOS technology

A new wideband low-distortion class A unitary gain voltage follower is presented in this brief. Based on a Gilberts translinear loop of four transistors, the proposed topology only includes high frequency n-p-n transistors in signal paths. The circuit has been simulated under /spl plusmn/1.5 V using the 0.8-/spl mu/m BiCMOS technology from AMS. Simulation results confirm low output distortion and high frequency operation performances. For a total power consumption of only 3 mW, the -3-dB bandwidth of the voltage transfer function is higher than 2.5 GHz with a 1-k/spl Omega/ loading resistance. The corresponding total harmonic distortion rate is lower than 0.06% when a 100-mV peak-to-peak input sinusoidal voltage is applied.

A new oscillator-based Random Number Generator

This paper proposes a low power, Truly Random Number Generator (TRNG) intended for a RFID tag application. We present here a new approach of the oscillator-based TRNG. The circuit relies on a system of jittered clocks that are being monitored by a clock arbiter-synchroniser, in order to have a random output signal without the use of a high speed jittered oscillator technique, that implies a significative increase the total power budget and a reduction in the output frequency. The system under study will be developed in AMS 0.35μm standard process for a 3.0V supply.

50 nA, 1 V nanowatt resistor-free compact CMOS current references

This paper presents a comparison between resistor-free nanowatt CMOS current references based on different topologies. All of these current references are designed to generate 50 nA currents under 1 V power supply. Designed in a standard 0.35 µm CMOS process, these current references showed low sensitivity with respect to the variations from power supply, fabrication process and temperature. EKV 2.0 MOS model which is able to provide continuous equation over different inversion levels (weak, moderate, and strong) is used in the process of analyzing these current references. Simulation results for these current references showed a max temperature coefficient of 0.07 %/°C over a temperature range of −40 °C to 125 °C and a minimum power supply as low as 0.75 V.

Integrated continuous microstimulation system for deep brain stimulation in rodent models of neurological disorders

This article proposes two prototypes in order to assure chronic deep brain stimulation in freely moving rodents, modeling the functional neurosurgical approach developed for the treatment of Parkinsons disease, which is now extending to a number of neurological and psychiatric diseases. This treatment is based on electrical simulation in a precise brain target with adapted parameters for each indication in terms of frequency, intensity and pulse width. The first topology, a discrete solution has been realized by using CMS technology and tested on a rat model of Parkinsons disease. The second one, even more miniaturized for a mouse application, is an all integrated solution with live tuning. A 0.35µm standard CMOS technology has been used for the realization of this last one solution with a final silicon ar ea of 620 ⋆ 516, 4µm2.

Electrical model of an NMOS body biased structure in triple-well technology under photoelectric laser stimulation

This study is driven by the need to optimize failure analysis methodologies based on laser/silicon interactions with an integrated circuit using a triple-well process. It is therefore mandatory to understand the behavior of elementary devices to laser illumination, in order to model and predict the behavior of more complex circuits. This paper presents measurements of the photoelectric currents induced by a pulsed-laser on an NMOS transistor in triple-well Psubstrate/DeepNwell/Pwell structure dedicated to low power body biasing techniques. This evaluation compares the triple-well structure to a classical Psubstrate-only structure of an NMOS transistor. It reveals the possible activation change of the bipolar transistors. Based on these experimental measurements, an electrical model is proposed that makes it possible to simulate the effects induced by photoelectric laser stimulation.

A 90-nm CMOS high efficiency on chip DC-DC converter for ultra-low power low cost applications

It is widely recognized that adaptive control of the power supply is one of the most effective variables to achieve energy-efficient computation. Most on-chip dc-dc conversion systems have relied on buck converters with off-chip LC filters. In this paper, we describe the development of fully integrated on-chip dc-dc down conversion system that combines switched-capacitor voltage divider and linear regulator. The converter was designed with 90-nm standard CMOS process. No external components are required. With an input voltage of 2.6V, the converter achieves step-down voltage conversion with an output voltage equal to 1.1V and a maximum efficiency of 63%. The converter employs a dynamic control loop to automatically adjust the switching frequency with the load current variation. Its switching frequency varies from 2MHz to 38MHz while load current is between 1mA and 16mA respectively. The use of switched-capacitor supply offers better efficiency than what is achievable with linear regulator alone.

771mV, 173nA, 90nm CMOS resistorless trimmable voltage reference

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.

A 90-nm CMOS resistor-free compact trimmable voltage reference for ultra-low power low cost applications

A low power voltage reference generator operating with a supply voltage ranging from 1.6V to 3.6V has been implemented in a 90-nm standard CMOS process. The reference is based on MOSFETs that are biased in the weak inversion region to consume nanowatts of power and uses no resistors. The maximum supply current at 3.6V and at 125°C is 173nA. It provides an 771mV voltage reference. A temperature coefficient of 7.5ppm/°C is achieved at best and 39.5ppm/°C on average, in a range from −40 to 125°C, as the combined effect of a suppression of the temperature dependence of mobility and the compensation of the threshold voltage temperature variation. The total block area is 0.03mm2.