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Dive into the research topics where Benjamin H. Ashmore is active.

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Featured researches published by Benjamin H. Ashmore.


IEEE Journal of Solid-state Circuits | 1991

An experimental 4 Mb flash EEPROM with sector erase

M. Mcconnell; Benjamin H. Ashmore; R. Bussey; Manzur Gill; Sung-Wei Lin; David J. Mcelroy; John F. Schreck; P. Shah; Harvey J. Stiegler; Phat C. Truong; A. L. Esquivel; J. Paterson; B. Riemenschneider

A 512K*8 flash EEPROM (electrically erasable programmable ROM) which operates from a single 5-V supply was designed and fabricated. A double-poly, single-metal CMOS process with a minimum feature size of 0.9 mu m was developed to manufacture the test vehicle, which resulted in a die size of 95 mm/sup 2/. The storage cell is 8.64 mu m/sup 2/ and consists of a one-transistor cell that uses a remote, scalable, tunnel diode for programming and erasing by Fowler-Nordheim tunneling. Process high-voltage requirements are relaxed by utilizing circuit techniques to alleviate the burden of high voltages. A segmented architecture provides the flexibility to erase any one sector (16 kB) or the entire chip during one cycle by an erase algorithm. The memory can be programmed one byte at a time, or the internal bit-line latches can be used to program a 256-B page in one cycle. A programming time of 10 ms is typical, which results in a write time of 40 mu s/B during page programming. The chip features an access time of 90 ns. >


international solid-state circuits conference | 1989

A 20 ns 1 Mb CMOS burst mode EPROM

Benjamin H. Ashmore; John F. Schreck; Phat C. Truong; Timmie M. Coffman; M. Andrews

A 64-K*16-b burst-mode EPROM (electrically programmable read-only memory) with a 20-ns statistical access time was achieved using 1.4- mu m lithography. An orthogonal x-drive and split array architecture allows efficient array segmentation utilizing a contactless buried diffusion memory cell. The resultant die size is 54.6 mm/sup 2/. The contactless, buried-diffusion memory cell is constructed using a self-aligned thick oxide (SATO) process which minimizes the array dimensions by requiring diffusion contacts only every 16 bits. The SATO array can be continuously biased without a power penalty because of its virtual ground array configuration. In many system applications, the burst mode memory configuration offers performance approaching maximum processor capability.<<ETX>>


Archive | 1990

Erasure of eeprom memory arrays to prevent over-erased cells

Benjamin H. Ashmore


Archive | 1991

Segmented, multiple-decoder memory array and method for programming a memory array

Sung-Wei Lin; John F. Schreck; Phat C. Truong; David J. Mcelroy; Harvey J. Stiegler; Benjamin H. Ashmore; Manzur Gill


Archive | 1988

Integrated programmable bit circuit with minimal power requirement

Benjamin H. Ashmore


Archive | 2003

Serial data input/output method and apparatus

Lee D. Whetsel; Benjamin H. Ashmore


Archive | 1988

Integrated programmable bit circuit using single-level poly construction

Benjamin H. Ashmore


Archive | 1988

Single-level poly programmable bit circuit

Benjamin H. Ashmore


Archive | 1993

Nonvolatile memory array wordline driver circuit with voltage translator circuit

John F. Schreck; Phat C. Truong; Benjamin H. Ashmore; Harvey J. Steigler


Archive | 1997

Data communication interface with memory access controller

Lee D. Whetsel; Benjamin H. Ashmore

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