Lee D. Whetsel

Adapting scan architectures for low power operation

Scan architectures are commonly used to test digital circuitry in integrated circuits. This paper describes a method of adapting conventional scan architectures such that they operate in a low power mode during test. The adapted scan architectures maintain the test times of the pre-adapted scan architectures. Also, the adaptation occurs in a manner that enables the test patterns of the pre-adapted scan architecture to be directly reusable in the adapted scan architecture.

An analysis of power reduction techniques in scan testing

Power consumption during scan testing is becoming a concern. Circuit switching activity during scan shifting is high and results in high average and instantaneous power consumption. This paper presents a scheme for reducing power and provides analysis results on an industrial design.

Towards a standard for embedded core test: an example

Integrated circuits are increasingly designed by embedding pre-designed reusable cores. IEEE P1500 Standard for Embedded Core Test (SECT) is a standard-under-development that aims at improving ease of reuse and facilitating interoperability with respect to the test of such core-based ICs, especially if they contain cores from different sources. This paper briefly describes IEEE P1500, and illustrates through a simplified example its dual compliance concept, its Scalable Hardware Architecture, and its Core Test Language. This paper provides a preliminary, unapproved view on IEEE P1500. The standard is still under development, and this paper only reflects the view of five active participants of the Standardization Committee on its current status.

An IEEE 1149.1 based test access architecture for ICs with embedded cores

This paper describes work at Texas Instruments regarding development of an IC architecture supporting hierarchical test access of embedded cores.

Addressable test ports an approach to testing embedded cores

Intellectual property (IP) core reuse is an emerging design style that will significantly accelerate the complexity of ICs. IP cores are predesigned circuit functions that can be selected from a library and integrated into system ICs to quickly provide highly complex silicon solutions. Low cost, efficient testing of system ICs designed with IP cores will be challenging.

A High Speed Reduced Pin Count JTAG Interface

This paper describes a high speed reduced pin count JTAG interface between a JTAG controller and target IC. Being able to access JTAG using only one or two pins allows JTAG to be designed into ICs that in the past have been resistant to JTAG, such as JEDEC standard package memories, microcontrollers, and mixed signal devices

A proposed standard test bus and boundary scan architecture

The author describes the test interface and boundary scan architecture proposed in the Joint Test Action Group (JTAG) 2.0 specification. The test access port described in the JTAG specification meets the requirements for a standard serial test interface. The architecture is flexible enough to support test structures ranging from boundary scan to the sophisticated maintenance and support structures required in the high end military and commercial arena of the electronics industry. Features discussed include the test access port, the instruction register, and the data register.<<ETX>>

Hierarchically accessing 1149.1 applications in a system environment

This paper presents a novel connection method that enables in 1149.1 test bus controller to hierarchically access and test 1149.1 circuits, independent of where the circuit exists within in an electronic system. The advantage of this approach is that it enables the 1149.1 test bus to be used hierarchically as a system level test bus, instead of only as a board level test bus.<<ETX>>

Improved boundary scan design

This paper describes work regarding improvements in boundary scan cell design. The results of this work provide an innovative way to implement boundary scan cells (BSCs) on IC input, output, and input/output (I/O) pins. The new cell designs provide; (1) reduced cell size, (2) reduced signalling delay, (3) support for I/sub DDQ/ testing, (4) protection of output buffers in the presence of shorts, and (5) a method of safely testing newly assembled boards.

Core test connectivity, communication, and control

This paper describes work at TI on a scan test architecture that provides test connectivity, communication, and control of embedded cores within system ICs. Low power scan testing and hierarchical reuse are also provided by the test architecture.