Benjamin J. Blalock

Designing 1-V op amps using standard digital CMOS technology

This paper addresses the difficulty of designing 1-V capable analog circuits in standard digital complementary metal-oxide-semiconductor (CMOS) technology, Design techniques for facilitating 1-V operation are discussed and 1-V analog building block circuits are presented. Most of these circuits use the bulk-driving technique to circumvent the metal-oxide-semiconductor field-effect transistor turn-on (threshold) voltage requirement. Finally, techniques are combined within a 1-V CMOS operational amplifier with rail-to-rail input and output ranges. While consuming 300 /spl mu/W, the 1-V rail-to-rail CMOS op amp achieves 1.3-MHz unity-gain frequency and 57/spl deg/ phase margin for a 22-pF load capacitance.

A 100-ps time-resolution CMOS time-to-digital converter for positron emission tomography imaging applications

An integrated CMOS subnanosecond time-to-digital converter (TDC) has been developed and evaluated for positron emission tomography (PET) front-end applications. The TDC architecture combines an accurate digital counter and an analog time interpolation circuit to make the time interval measurement. The dynamic range of the TDC is programmable and can be easily extended without any timing resolution degradation. The converter was designed to operate over a reference clock frequency range of 62.5 MHz up to 100 MHz and can have a bin size as small as 312.5 ps LSB with 100-ns conversion times. Measurements indicate the TDC achieves a DNL of under /spl plusmn/0.20 LSB and INL less than /spl plusmn/0.30 LSB with an rms timing resolution of 0.312 LSB (97.5 ps), very close to the theoretical limit of 0.289 LSB (90 ps). The design is believed to be the first fully integrated CMOS subnanosecond TDC used in PET medical imaging and the first realization of a CMOS TDC that achieves an rms timing resolution below 100 ps within a 100-ns conversion time.

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

A low-voltage, bulk-driven MOSFET current mirror for CMOS technology

A bulk-driven, MOSFET current mirror is described which is capable of operating at power supplies down to 1 V using standard CMOS technologies with threshold voltages in the range of /spl plusmn/0.8 V. The bulk-driven MOSFET configuration removes the requirement that the input voltage of the current mirror equal V/sub GS/>V/sub T/. At V/sub DD//V/sub SS/ of+0.75 V/-0.75 V, measurements on simple current mirrors using this new technique require only about 0.1 V across the input device of the current mirror circuit and exhibit saturation voltages on the output device of the current mirror comparable to that of standard simple current mirrors. The operation and first-order models for the bulk-driven MOSFET are presented in this paper along with the operation and experimental results of a simple, bulk-driven mirror.

A di/dt Feedback-Based Active Gate Driver for Smart Switching and Fast Overcurrent Protection of IGBT Modules

This paper presents an active gate driver (AGD) for IGBT modules to improve their overall performance under normal condition as well as fault condition. Specifically, during normal switching transients, a di/dt feedback controlled current source and current sink is introduced together with a push-pull buffer for dynamic gate current control. Compared to a conventional gate drive strategy, the proposed one has the capability of reducing the switching loss, delay time, and Miller plateau duration during turn-on and turn-off transient without sacrificing current and voltage stress. Under overcurrent condition, it provides a fast protection function for IGBT modules based on the evaluation of fault current level through the di/dt feedback signal. Moreover, the AGD features flexible protection modes, which overcomes the interruption of converter operation in the event of momentary short circuits. A step-down converter is built to evaluate the performance of the proposed driving schemes under various conditions, considering variation of turn-on/off gate resistance, current levels, and short-circuit fault types. Experimental results and detailed analysis are presented to verify the feasibility of the proposed approach.

Active Gate Driver for Crosstalk Suppression of SiC Devices in a Phase-Leg Configuration

In a phase-leg configuration, the high-switching-speed performance of silicon carbide (SiC) devices is limited by the interaction between the upper and lower devices during the switching transient (crosstalk), leading to additional switching losses and overstress of the power devices. To utilize the full potential of fast SiC devices, this paper proposes two gate assist circuits to actively suppress crosstalk on the basis of the intrinsic properties of SiC power devices. One gate assist circuit employs an auxiliary transistor in series with a capacitor to mitigate crosstalk by gate loop impedance reduction. The other gate assist circuit consists of two auxiliary transistors with a diode to actively control the gate voltage for crosstalk elimination. Based on CREE CMF20120D SiC MOSFETs, the experimental results show that both active gate drivers are effective to suppress crosstalk, enabling turn-on switching losses reduction by up to 17%, and negative spurious gate voltage minimization without the penalty of decreasing the switching speed. Furthermore, both gate assist circuits, even without a negative isolated power supply, are more effective in improving the switching behavior of SiC devices in comparison to the conventional gate driver with a -2 V turn-off gate voltage. Accordingly, the proposed active gate assist circuits are simple, efficient, and cost-effective solutions for crosstalk suppression.

Body-driving as a low-voltage analog design technique for CMOS technology

This paper presents an overview of circuit topologies for achieving low-voltage analog designs using body-driving techniques. A new and novel low-voltage Class AB output stage is presented along with topologies for amplifiers and a four quadrant multiplier. A discussion of the application of body-driving in a silicon-on-insulator (SOI) technology is also included.

Evaluation of 600 V cascode GaN HEMT in device characterization and all-GaN-based LLC resonant converter

In recent years, Si power MOSFET is approaching its performance limits, and Gallium Nitride (GaN) HEMT is getting mature. This paper evaluates the 600 V cascode GaN HEMT performance, and compares it with the state-of-the-art Si CoolMOS in LLC resonant converter. First, the static characterization of 600 V cascode GaN HEMT is described in different temperatures. The switching performance is tested by a double pulse tester to provide the turn-off loss reference to the design of LLC resonant converter. Second, a 400 V-12 V/300 W/1 MHz all-GaN-based converter with the 600 V cascode GaN HEMT is compared with a Si-based converter with the 600 V Si CoolMOS. The device output capacitance is a key factor in the design and loss analysis of LLC resonant converter. The design results show that the total GaN device loss of the all-GaN-based converter can be improved by 42% compared with the total Si device loss. Finally, both 400 V-12 V/300 W/1 MHz Si-based and GaN-based LLC resonant converter prototypes are tested and compared with waveforms and efficiency curves.

Evaluation and comparison of silicon and gallium nitride power transistors in LLC resonant converter

Silicon Power MOSFETs, with more than thirty years of development, are widely accepted and applied in power converters. Gallium Nitride (GaN) power devices are commercially available in recent years [1], but the device performance and application have not been fully developed. In this paper, GaN devices are compared with state-of-art Si devices to evaluate the device impact on soft-switching DC-DC converters, like LLC resonant converter. The analytical approach of device selection and comparison are conducted and loss related device parameters are derived. Total device losses are compared between Si and GaN based on these parameters. GaN shows less loss compared with Si, yielding approximately a 20% reduction of total device loss. Two 300 W, 500 kHz, 48 V-12 V GaN-based and Si-based converter prototypes are built and tested. Since the body diode forward voltage drop of GaN device is high, the dead time is adjusted to minimize the body diode conduction period. The peak efficiency of the GaN-based converter is 97.5%, and the full load efficiency is 96.1%, which is around 0.3% higher than the Si-based converter at full load. The test results shows that, although GaN device has lower loss, the improvement of converter efficiency is not much. The reason is that the transformer loss accounts for more than 60% of total loss. Therefore, a transformer which fits the GaN device characteristic need to be further investigated.

Analysis of the switching speed limitation of wide band-gap devices in a phase-leg configuration

Advanced power semiconductor devices, especially wide band-gap devices, have inherent capability for fast switching. However, due to the limitation of gate driver capability and the interaction between two devices in a phase-leg during switching transient (cross talk), the switching speed is slower than expected in practical use. This paper focuses on identifying the key limiting factors for switching speed. The results provide the basis for improving gate drivers, eliminating interference, and boosting switching speed. Based on the EPC2001 Gallium Nitride transistor, both simulation and experimental results verify that the limiting factors in the gate loop include the pull-up (-down) resistance of gate driver, rise (fall) time and amplitude of gate driver output voltage; among these the rise (fall) time plays the primary role. Another important limiting factor of device switching speed is the spurious gate voltage induced by cross talk between two switches in a phase-leg. This induced gate voltage is not only determined by the switch speed, but also depends on the gate loop impedance, junction capacitance, and operating conditions of the complementary device.