Mohammad Mojarradi

A miniaturized neuroprosthesis suitable for implantation into the brain

This paper presents current research on a miniaturized neuroprosthesis suitable for implantation into the brain. The prosthesis is a heterogeneous integration of a 100-element microelectromechanical system (MEMS) electrode array, front-end complementary metal-oxide-semiconductor (CMOS) integrated circuit for neural signal preamplification, filtering, multiplexing and analog-to-digital conversion, and a second CMOS integrated circuit for wireless transmission of neural data and conditioning of wireless power. The prosthesis is intended for applications where neural signals are processed and decoded to permit the control of artificial or paralyzed limbs. This research, if successful, will allow implantation of the electronics into the brain, or subcutaneously on the skull, and eliminate all external signal and power wiring. The neuroprosthetic system design has strict size and power constraints with each of the front-end preamplifier channels fitting within the 400 /spl times/ 400-/spl mu/m pitch of the 100-element MEMS electrode array and power dissipation resulting in less than a 1/spl deg/C temperature rise for the surrounding brain tissue. We describe the measured performance of initial micropower low-noise CMOS preamplifiers for the neuroprosthetic.

Modeling spiral inductors in SOS processes

Existing models for simulating spiral inductors fabricated in silicon processes are outgrowths of the PI structure originally employed by Nguyen and Meyer (1990). This structure and its subsequent elaborations work well for inductors in which the dominant loss mechanism is the underlying substrate. For newer processes with very high resistivity or insulating substrates such as Silicon-on-sapphire however, the model breaks down since inductor quality factor Q is then determined predominantly by series trace resistance. Models suitable for use in such processes are proposed and compared with measured data. The new models contain only four to six elements and, unlike the classic PI model, provide a broadband match to measured impedance behavior in both differentially driven and single-ended circuit applications.

A high voltage Dickson charge pump in SOI CMOS

An improved charge pump that utilizes a MOSFET body diode as a charge transfer switch is discussed. The body diode is characterized and a body diode model is developed for simulating the charge pump circuit. An increase in voltage pumping gain for a silicon-on-insulator (SOI) Dickson charge pump is demonstrated when compared with a traditional bulk CMOS Dickson charge pump. A 6-stage Dickson charge pump was designed to produce a 20 V output from a 3.3 V supply, using a 4 MHz, two-phase non-overlapping clock signal driving the charge pump. The design was fabricated in a 0.35 /spl mu/m partially depleted SOI CMOS process. An efficiency of 72% is achieved at a load current of approximately 20 /spl mu/A.

The Four-Gate Transistor

The four-gate transistor or G4-FET combines MOSFET and JFET principles in a single SOI device. Experimental results reveal that each gate can modulate the drain current. Numerical simulations are presented to clarify the mechanisms of operation. The new device shows enhanced functionality, due to the combinatorial action of the four gates, and opens rather revolutionary applications.

SILICON-BASED INTEGRATED MOSFETS AND MESFETS: A NEW PARADIGM FOR LOW POWER, MIXED SIGNAL, MONOLITHIC SYSTEMS USING COMMERCIALLY AVAILABLE SOI

Metal Semiconductor Field Effect Transistors fabricated using compound semiconductor materials have important applications in high-speed/low-noise communication systems. However, their integration densities are low compared to silicon technologies, and it is difficult to combine them with conventional CMOS for single-chip, mixed-signal circuit applications. In this paper we describe how silicon-on-insulator MESFETs can be fabricated alongside conventional MOSFETs using a commercially available silicon-on-insulator foundry. The process flow for the integrated MOSFETS and MESFETs is presented. Measurements from MESFETs fabricated using a commercial foundry demonstrate good depletion-mode device operation. The measured data confirms a square-law behavior for the saturated drain current, which can be reproduced using readily available MESFET models for Spice circuit simulation. The Spice model is applied to a simple differential-pair amplifier and the modeled results compared to measured data.

Compact Modeling of LDMOS Transistors for Extreme Environment Analog Circuit Design

The cryogenic characterization (93 K/-180°C to 300 K/27°C) and compact modeling of a high-voltage (HV) laterally diffused MOS (LDMOS) transistor that exhibits carrier freeze-out are presented in this paper. Unlike low-voltage MOS devices, it was observed that HVMOS structures experience freeze-out effects at much higher temperatures, resulting in an output current roll-off beyond a transition temperature. Standard compact models generally do not guarantee performance below 218 K (-55°C), and freeze-out effects are certainly not incorporated in them. This causes the models to fail to track at lower temperatures, and designers relying on these models would be misled. In this paper, the temperature-scaling equations of the MOS Model 20 LDMOS model are modified to reflect the device operation down to 93 K, which is sufficient for designing sensor interface circuitry for lunar applications. The model is then validated against an LDMOS device designed by engineers at the Jet Propulsion Laboratory, using the IBM SiGe 5AM process. A modified parameter extraction procedure has also been developed. This generalized approach is compact model friendly and can also be implemented for other standard models. Analog circuits designed with this new model are currently being tested at the International Space Station.

A resonant switch for LNA protection in watt-level CMOS transceivers

An integrated resonant switch designed to protect low-noise amplifier (LNA) circuits in CMOS transceivers is reported. The design implements the receive-path portion of a transmit/receive switch protecting 3-V-process transistors from 5 W (22-V peak) transmit signals while simultaneously helping to achieve a good LNA noise figure on receive and low power loss on transmit. Since the approach is to combine an LNAs matching network and switch functions, the design has no traditional insertion loss on receive. The effective loss to the transmitted signal is less than 0.5 dB using moderate quality inductors (Q>6) and 0.1 dB using Q=12 inductors achievable in most RF-aware CMOS silicon-on-insulator foundries at UHF through S-band frequencies.

The operation of 0.35 μm partially depleted SOI CMOS technology in extreme environments

Abstract We evaluate the usefulness of partially depleted SOI CMOS devices fabricated in a 0.35 μm technology on UNIBOND material for electronics applications requiring robust operation under extreme environment conditions consisting of low and/or high temperature, and under substantial radiation exposure. The threshold voltage, effective mobility, and the impact ionization parameters were determined across temperature for both the nFETs and the pFETs. The radiation response was characterized using threshold voltage shifts of both the front-gate and back-gate transistors. These results suggest that this 0.35 μm partially depleted SOI CMOS technology is suitable for operation across a wide range of extreme environment conditions consisting of: cryogenic temperatures down to 86 K, elevated temperatures up to 573 K, and under radiation exposure to 1.3 Mrad(Si) total dose.

A new approach to designing electronic systems for operation in extreme environments: Part II - The SiGe remote electronics unit

We have presented the architecture, simulation, packaging, and over-temperature and radiation testing of a complex, 16-channel, extreme environment capable, SiGe Remote Electronics Unit containing the Remote Sensor Interface ASIC that can serve a wide variety of space-relevant needs as designed. These include future missions to the Moon and Mars, with the additional potential to operate in other hostile environments, including lunar craters and around the Jovian moon, Europa. We have expanded on the previous introduction of the RSI to show the validity of the chip design and performance over an almost 250 K temperature range, down to 100 K, under 100 krad TID radiation exposure, with SEL immunity and operability in a high-flux SET environment.

A new approach to designing electronic systems for operation in extreme environments: Part I - The SiGe Remote Sensor Interface

We have described the modeling, circuit design, system integration, and measurement of a Remote Sensor Interface (Figure 20) that took place over a span of 5 years and 8 fabrication cycles. It was conceived as part of the Multi-Chip Module (MCM) shown in Figure 21, which also includes a digital control chip for clocking, programming, and read-out. Further work beyond the scope of this was performed to validate the RSI for the extreme environmental conditions of a lunar mission, and individual blocks are presently.