S.C. Terry

A custom mixed-signal CMOS integrated circuit for high performance PET tomograph front-end applications

A custom mixed-signal CMOS integrated circuit has been developed for high performance PET tomograph front-end applications. The ASIC contains four differential, variable-gain, constant bandwidth, amplifiers to receive buffered PMT voltage pulses. All four amplified PMT signals are summed by adding their outputs and feeding this sum to the timing channel of the ASIC. The timing channel, which consists of a constant fraction discriminator and sub-nanosecond time to digital converter, offers excellent PET count rate performance and random noise reduction through low deadtime (100 ns) and excellent tuning resolution (312.5 ps). Amplified PMT signals are also distributed to energy processing channels for lowpass filtering, and buffering for subsequent digitization by external ADCs. The ASIC offers substantial size, power, and cost reductions over existing PET front-end discrete designs. Fabricated in a 5 V, 0.5 /spl mu/m, triple metal, double poly, n-well CMOS process, the new ASIC has a die size of 20 mm/sup 2/ and dynamic power dissipation under 425 mW.

Comparison of a BSIM3V3 and EKV MOSFET model for a 0.5 /spl mu/m CMOS process and implications for analog circuit design

A BSIM3V3 and EKV model for a standard 0.5 um CMOS process has been evaluated for analog applications. Critical small-signal parameters including output conductance and transconductance efficiency were simulated for devices with gate lengths ranging from 0.5 um to 33 um. In addition, the small-signal parameters were measured on test devices with similar dimensions. The results highlight the difficulty of obtaining a model that accurately predicts the operation of low voltage analog circuits.

Integrated Circuit Biosensors Using Living Whole-Cell Bioreporters

A low-power CMOS bioluminescent bioreporter integrated circuit (BBIC) is designed and fabricated for use in electronic/biological chemical sensing. The bioreporters are placed on a CMOS integrated circuit (IC) that detects bioluminescence, performs signal processing and produces a digital output pulse with a frequency that is proportional to the concentration of the target substance. The digital output pulse that contains the sensor information can then be transmitted to a remote location either wirelessly or via a data cable. The basic building blocks of the integrated circuit are the microluminometer and the transmitter. The microluminometer includes an integrated photodetector and a signal processor and is housed in a rugged inexpensive package that can be used in many remote applications in hazardous environmental monitoring. The total power consumption of the entire signal processing circuitry including the photodiodes is 3 mW from a 3.3-V power supply. This is lowered by a factor of 3 when compared to previous versions of the BBIC. In addition, it also integrates all features of detection, processing and data transmission into one small element. The bioreporter typically contains the luxCDABE reporter genes. The close proximity of the bioreporter and the sensing element eliminates the need for complex instrumentation to channel light from the bioreporters to the microluminometer. This paper presents an integrated CMOS microluminometer realized in 0.35-mum CMOS process and optimized for the detection of low-level bioluminescence as part of the BBIC. A flow-through test system was designed to expose the BBIC system composed of the microluminometer and the bioreporter Pseudomonas fluorescens 5RL to salicylate for determination of analytical benchmark data. The results obtained from the experiment are currently being used to study enclosures and micro-environment configurations for field-deployable BBICs for environmental monitoring

Development of robust analog and mixed-signal electronics for extreme environment applications

The Integrated Circuits and Systems Laboratory at the University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. In this paper, we present system level and transistor level extreme environment design techniques and measurement results from several test circuits. The design techniques focus on developing high performance operational transconductance amplifiers (OTAs) and op-amps that can operate over a wide temperature range. The test circuits include a 3.3-V ping-pong op-amp, a 3.3-V rail-to-rail I/O op-amp capable of driving resistive loads, and a temperature stable voltage reference and current reference.

Time-domain noise analysis of linear time-invariant and linear time-variant systems using MATLAB and HSPICE

A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear time-variant (LTV) systems. MATLAB is used to generate a set of representative noise signals, which are imported into HSPICE for simulation. Once the simulations are complete the results are read back into MATLAB and ensemble statistics are calculated. The MATLAB-generated noise signals have a user-defined white-noise floor and flicker-noise corner frequency and thus are suitable for modeling a wide variety of electronic components, including CMOS transistors and resistors. Simulation results of the time-dependent output noise of a gated integrator and the timing resolution of a gated integrator/comparator detector are presented to highlight both the utility and the versatility of the tool.

Time-domain noise analysis of linear time-Invariant and linear time-variant systems using MATLAB and HSPICE

A custom simulation tool that combines HSPICE and MATLAB to enable time-domain noise analysis is reported. The simulation technique is based on computing the statistics of a random process by ensemble averaging and is applicable to both linear time-invariant (LTI) and linear time-variant (LTV) systems. MATLAB is used to generate a set of representative noise signals, which are imported into HSPICE for simulation. Once the simulations are complete the results are read back into MATLAB and ensemble statistics are calculated. The MATLAB-generated noise signals have a user-defined white-noise floor and flicker-noise corner frequency and thus are suitable for modeling a wide variety of electronic components, including CMOS transistors and resistors. Simulation results of the time-dependent output noise of a gated integrator and the timing resolution of a gated integrator/comparator detector are presented to highlight both the utility and the versatility of the tool.

Adaptive gate biasing: a new solution for body-driven current mirrors

A new body-driven current mirror that utilizes an adaptive gate bias to provide accurate operation over a wide range of bias currents is presented. The proposed current mirror can operate with an input and output voltage compliance of VDSAT with no level shifting; thus it is suitable for operation at power supply voltages ≤ 1 V. Measurement results from test circuits implemented in a conventional partially depleted SOI CMOS process show that an nMOS body-driven current mirror that uses the proposed design technique operates reliably over the range 100 nA--1 mA---a four-decade current range which includes the weak, moderate, and strong inversion regions for the devices tested.

Temperature-compensated reference circuits for SOI

Two novel reference circuits that exploit unique aspects of SOI technology are reported. The first is a voltage reference based on the G/sup 4/-FET, a new four-gate transistor possible only in SOI; which achieves a temperature-compensated output voltage without the use of the standard bandgap architecture. The second is a current reference that uses the zero leakage p-well resistor available in many SOI technologies to achieve a low-level, temperature-stable reference current that exceeds the specifications of bulk CMOS low-level current references reported in the literature. Both reference circuits have been implemented in a standard 3.3-V/0.35-/spl mu/m partially depleted (PD)-SOI process.

Development of robust analog electronics at the University of Tennessee for NASA/JPL extreme environment applications

The INSYTE (Integrated Circuits and Systems) Laboratory at The University of Tennessee is currently investigating robust CMOS analog and mixed-signal circuit design techniques for extreme environments. This work is being targeted for Mars surface applications where the temperature can vary from -1200/spl square/C to +20/spl square/C depending on time of day and location. In this paper we present both robust analog design techniques and measurement results from several test circuits. The design techniques focus on developing high performance OTAs and op-amps that can operate over a wide temperature range. The test circuits include a 3.3 V ping-pong op-amp and a 3.3 V rail-to-rail I/O op-amp capable of driving resistive loads.

1/f Noise and DC Characterization of Partially Depleted SOI N-and P-MOSFETs from 20 º C-250 º C

A summary of measured small-signal parameters and low frequency noise characterized over temperature is presented for N- and P- MOSFETs fabricated in a partially depleted SOI 0.8 mum process. Small-signal dc parameters critical in analog circuit design are reported including device transconductance efficiency (gm/Id), output resistance (rds), and threshold voltage (Vt). These parameters are summarized as a function of both gate length (0.8mum, 2.0mum, 5.0mum, and 20mum) and temperature (20deg to 300degC). Noise characterization of these devices is also presented with an emphasis on flicker noise over temperature (20deg to 250degC). Data is presented in terms of both drain current and inversion coefficient, where appropriate. Use of this information provides the designer with an excellent tool for estimating analog circuit performance in applications where wide temperature range performance is required