Benoit Provost

On-chip ramp generators for mixed-signal BIST and ADC self-test

A practical approach to generate on-chip precise and slow analog ramps, intended for time-domain analog testing, monotonicity and histogram-based tests of ADCs is proposed. The technique uses an analog discrete-time adaptive scheme to calibrate the ramp generator. The lowest slope is 0.4V/ms. Three implementations are presented for different levels of accuracy and complexity. Measurement results show excellent accuracy and programmability, up to only 0.6% of slope error and maximum integral nonlinearity error of /spl plusmn/175/spl mu/V. Experimental and theoretical results are in good agreement.

Auto-calibrating analog timer for on-chip testing

A practical approach for generating precise and slow analog ramps to be used for time-domain analog testing and for monotonicity and histogram test of ADCs is presented. The technique uses a discrete-time adaptive scheme to calibrate the ramp generator. Two implementations of the approach are proposed: one is entirely single-ended and the second uses a pseudo-differential-based offset cancellation scheme. The first implementation has been implemented in 2 mm technology and experimental results are in agreement with simulations yielding a slope error of 1.5% and distortion of 0.2%.

A practical self-calibration scheme implementation for pipeline ADC

An efficient pipeline analog-to-digital converter (ADC) self-calibration implementation is presented. The technique uses a highly linear on-chip analog ramp generator, performs a simplified on-chip integral nonlinearity (INL) measurement, and extracts the compensation coefficients. Except for the ramp generator, the whole calibration is performed in the digital domain and is done at the nominal ADC speed (at-speed). The approach does not require any modification to the original analog section of the ADC. The INL measurement can be carried off-chip to simplify the production testing or to perform performance verification in the application environment. Simulation and measurement results show an INL improvement of more than 2 bits (from /spl plusmn/2.1 LSB to /spl plusmn/0.5 LSB).

AC IO loopback design for high speed /spl mu/processor IO test

This work presents the next generation AC IO loopback design for two Intel processor architectures. Both designs detect I/O defects with 20 ps resolution and 50 ps jitter for up to 800 MHz bus speed. Even though the implementations differ in some aspects to accommodate two different bus architectures, the same prudent considerations for high speed operation, minimum test inaccuracy, and low implementation costs apply to both.

External Loopback Testing Experiences with High Speed Serial Interfaces

Data eye margin test used in conjunction with loopback configuration has become a popular design for test (DFT) based test method for high speed links. This paper summarizes the DFT circuitry and test methods for supporting high speed serial interfaces (e.g. S-ATA,). The challenges of no-touch test methods in an external loopback environment are discussed. We close with a summary of our manufacturing experiences and directions for future improvement.

I/O self-leakage test

This work presents the implementation of the self-leakage test, a new approach for unconnected I/O leakage testing. It provides a path for leakage current through the on-chip leakers and uses the voltage drop at the pad to detect a pass/fail condition. A detailed methodology for defining the self-leakage test specifications has been developed. Preliminary silicon data shows that self-leakage test methodology provide a viable method for high-volume monitoring of I/O leakage at minimal on-die DFT (design-for-test) overhead.

Adaptive analog timer for on-chip testing

A practical approach for generating precise and slow analog ramps to be used for on-chip time-domain analog testing and for monotonicity and histogram test of ADCs is introduced. The calibration uses a discrete-time adaptive scheme. Two implementations of the approach are proposed; one is continuous-time and the second is discrete-time. Convergence criteria are defined. Results from a fabricated circuit in a low-cost 2 /spl mu/m technology are in agreement with theoretical results.

A unified approach for a time-domain built-in self-test technique and fault detection

Being able to fully test a circuit is an important issue for quality manufacturing. Unlike fault analysis for digital circuits, analog fault analysis has been comparatively slow to evolve. The purpose of this paper is to study the feasibility of the time domain response analysis as a test method for analog circuits. The approach was to first study the fault coverage obtained by testing the main parameters of the new NGCC amplifier, which shows the feasibility of built-in self test in time-domain. A circuit macromodel to implement a time-domain built-in self-test circuit was then proposed.