Anne Meixner

Weak write test mode: an SRAM cell stability design for test technique

The detection of cell stability and data retention faults in SRAMs has been a time consuming process. In this paper we discuss a new design for test technique called Weak Write Test Mode (WWTM). This technique applies test circuitry which attempts to overwrite the data stored in SRAM cells. It is designed so that only defective cells are overwritren. The resulting test has a shorter test time and improved detection capability. In addition, WWTM has a low silicon area cost and no impact on product performance. Silicon results are reported.

Elimination of traditional functional testing of interface timings at intel

This work summarizes the design for test (DFT) circuitry and test methods that enabled Intel to shift away from traditional functional testing of I/Os. This shift was one of the key enablers for automatic test equipment (ATE) re-use and the move to lower capability (& cost) structural test platforms. Specific examples include circuit implementations from the Pentium/sup /spl reg// 4 processor, high volume manufacturing (HVM) data, and evolutionary changes to address key learnings. We close with indications of how this can be extended to cover the next generation high speed serial like interfaces.

An industrial case study of analog fault modeling

Analog fault modeling (AFM) provides a quantitative measure of quality and insight into defective device behavior. However, the high computational burden typically associated with fault simulation makes it unappealing for industrial applications. We propose an efficient methodology to reduce computational burden of the AFM method by exploiting the hierarchical nature of process variation. We apply the proposed methodology on an industrial SerDes TX Driver circuit and achieve 98% simulation time reduction. We quantify defect impact with a defect severity measure.

External Loopback Testing Experiences with High Speed Serial Interfaces

Data eye margin test used in conjunction with loopback configuration has become a popular design for test (DFT) based test method for high speed links. This paper summarizes the DFT circuitry and test methods for supporting high speed serial interfaces (e.g. S-ATA,). The challenges of no-touch test methods in an external loopback environment are discussed. We close with a summary of our manufacturing experiences and directions for future improvement.

An IDDQ BIST approach to characterize phase-locked loop parameters

In this work, a new IDDQ built-in self-test (BIST) solution is proposed to provide accurate on-chip current measurements for phase-locked loops (PLLs) found in deep-submicron system-on-chip (SoC) products. The proposed method characterizes PLL loop parameters to increase test quality with minimum additional test time and 4.5% accuracy in IBM 65 nm technology. A self-correction mechanism accompanies the proposed BIST to recover performance variations resulting from excessive process variation found in high-volume manufacturing (HVM). The proposed IDDQ BIST circuits performance is evaluated in silicon using 0.18μm technology and achieves 2% accuracy with only 1.7% additional PLL area overhead. Extensions to other analog mixed signal circuit blocks should be possible.

Improving IO test and system evaluation via data sharing

High speed I/O circuits are becoming increasingly critical as technology scales to increase system bandwidth and decrease power dissipation, die area and system cost. Highly integrated SOCs are currently equipped with large numbers of serial links to enable processing of high bandwidth data streams. There are two major challenges to continued scaling of highspeed I/Os: band-limited channels and timing uncertainty that require a good knowledge on customer system usage. In addition the increase push for customer differentiation and OEMs pushing more designs to low cost and less skilled design teams adds to the challenge. Adequate learning data sharing between customers and silicon provider is key in these emerging markets to meet quality and Time to Market targets.

Design considerations and DFT to enable testing of digital interfaces

In the last 15 years, the specifications for digital interfaces have evolved significantly, from specifying only nominal or typical values to specifying extreme maximum or minimum values that are observable at the pins of the device to values that are not directly observable at the pins of the device. There has been a corresponding evolution of high volume manufacturing (HVM) testing methods. This tutorial paper summarizes the various digital interfaces specifications, the techniques used to test then, and the associated design considerations and design for test (DFT) circuitry. The example specifications and test data are from my experience on Intel Pentium-Pro, Pentium III and Pentium 4 microprocessors.