Kyoohyun Lim

A low-noise phase-locked loop design by loop bandwidth optimization

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

A 2x2 MIMO Tri-Band Dual-Mode Direct-Conversion CMOS Transceiver for Worldwide WiMAX/WLAN Applications

This paper describes a fully integrated 130 nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The proposed transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. With carefully chosen LO frequency planning, the transceiver is capable of operating at 2.3-2.7 GHz, 3.3-3.9 GHz, and as well as 5.1-5.9 GHz bands covering whole frequency spectrum of fixed and mobile WiMAX and WLAN. The measured noise figure of the receiver is 3.6-4.2, 4.2-4.7, and 5.4-6.2 dB for each 2/3/5 GHz bands respectively. The measured PLL phase noise from 1 kHz to 10 MHz is 0.5/0.8/0.95 rms degree for 2/3/5 GHz bands respectively. The transceiver ensures low EVM over the wide dynamic range due to linear RX and TX signal paths and low integrated PLL phase noise characteristics.

A Fully Integrated Direct-Conversion Receiver for CDMA and GPS Applications

This paper describes a fully integrated zero-IF receiver for cellular CDMA and GPS applications. The single-chip zero-IF receiver integrates the entire signal path for CDMA and GPS bands, including a low-noise amplifier (LNA), I/Q down-converters, baseband channel selection filters (CSFs), a voltage-controlled oscillator (VCO), and a local oscillator (LO) distribution circuit for each band. The cellular-band LNA achieves a noise figure (NF) of 1.2 dB, input third-order intercept point (IIP3) of 11 dBm, and gain of 15.5 dB. Cellular I/Q down-converter and baseband circuitries show 9-dB composite NF, 9 dBm IIP3 and 60-dBm input second-order intercept point (IIP2) without IIP2 calibration. The measured LO leakage is less than -110 dBm at LNA input. The phase noise of the cellular VCO is -134 dBc/Hz at 900-kHz offset with 1.76-GHz carrier frequency. Total GPS signal path achieves NF of 1.7 dB and gain of 74 dB with 42-mA current. The receiver is fabricated in a 0.35-mum SiGe BiCMOS process and packaged in a 6 mm times 6 mm 40-pin micro-lead-frame. Handset measurements report that the receiver meets or exceeds all of the CDMA-2000 requirements

A fully integrated CMOS RF front-end with on-chip VCO for WCDMA applications

Increasing demand on the broadband data transmission via mobile phones drives standards for the third generation cellular phones. Both wide-band CDMA (WCDMA) and CDMA2000 compliant cellular phones make possible full-bandwidth Internet access. A high level of integration is necessary because of low power and low cost requirements, making CMOS implementation attractive. In the WDMA RF receiver, sensitivity, single-tone desensitization, and intermodulation rejection are the key performance indicators and should be minimized by controlling the parameters such as noise figure (NF), input-referred 3/sup rd/-order intercept (IIP3), gain distributions, and voltage-controlled oscillator (VCO) phase noise. Because of the high data rate supported by the WCDMA standard, more stringent control over the parameters is required. An on-chip VCO is helpful, because it eliminates I/O buffers and reduces substrate noise injection and power consumption.

A High IIP2 Direct-Conversion Receiver Using Even-Harmonic Reduction Technique for Cellular CDMA/PCS/GPS Applications

A high IIP2 direct-conversion receiver for cellular CDMA/PCS/GPS has been developed in a 0.35 mum SiGe BiCMOS process. This receiver consists of a RF front-end chip and a base-band chip. The RF front-end chip includes three LNAs, three mixer cores with a common output stage, and LO distribution blocks. The base-band chip includes a channel selection filter, an output buffer, and a DC calibration block. To achieve high IIP2 performance, an even-harmonic reduction technique is proposed based on a simplified analysis of second-order intermodulation. A 40-dB improvement of the IIP2 performance is accomplished by this technique, which reduces sensitivity to operating conditions and to output load mismatches. This receiver also attains high IIP3 and a low-noise figure. Measurement results show 71 dBm IIP2, -1.3 dBm IIP3, and 2.4 dB NF for Cellular CDMA; 68 dBm IIP2, - 3.7 dBm IIP3, and 2.9 dB NF for PCS; and 26 dBm IIP2 -30 dBm IIP3, and 2 dB NF for GPS.

A fully-integrated low power direct conversion transmitter with fractional-N PLL using a fast AFC technique for CDMA applications

The paper presents a fully integrated low power direct conversion transmitter IC for CDMA applications. To reduce the power consumption and reduce switching time, a fractional-N frequency synthesizer with an internal VCO is integrated into the transmitter IC and an N-target algorithm is proposed to implement automatic frequency calibration (AFC). Total locking time is approximately 200 /spl mu/s, including 80 /spl mu/s AFC lock time. Total current consumption for -80 dBm, -10 dBm, and 8 dBm output power are 27 mA, 33 mA, and 60 mA, respectively. This chip is housed in a small 5 mm /spl times/ 5 mm 32 pin MLF package.

Low noise clock synthesizer design using optimal bandwidth

This paper presents a salient method to design a low noise clock synthesizer for high-speed data processing applications. The proposed design method optimizes the loop bandwidth by using a discrete-time analysis of a PLL and minimizes the clock synthesizer output jitter. Computer simulation is performed and simulation results strongly support the theoretical analysis. A 900 MHz clock synthesizer is experimentally designed and shows the minimum jitter at the optimum bandwidth obtained from the analysis.

A direct-conversion CMOS RF receiver reconfigurable from 2GHz to 6GHz

A CMOS direct-conversion receiver with only one signal path is reconfigurable from 2 GHz to 6 GHz in the RF band and from 3.6 MHz to 54 MHz in the channel bandwidth. By employing a voltage feedback in a common-gate low-noise amplifier (LNA), the input matching of the LNA can be reconfigured for each RF band by simply changing the resonant frequency of load network. Implemented in a 0.18 mum 1P5M RF CMOS technology, the whole receive path shows 4.6~5.6 dB noise figure.

A 2×2 MIMO tri-band dual-mode CMOS transceiver for worldwide WiMAX/WLAN applications

This paper describes a fully integrated 130nm CMOS 2×2 MIMO tri-band dual-mode transceiver for fixed and mobile WiMAX and IEEE 802.11a/b/g/n applications. The transceiver features reduced RF interface (only 4 RF pins) with the wideband circuit topology of the LNA and drive amplifier that minimizes the performance degradation. The measured receive path NF is 3.6~4.2, 4.2~4.7, and 5.4~6.2dB for the 2/3/5GHz bands respectively. The measured integrated phase noise from 1kHz to 10MHz is 0.5/0.8/0.95 rms degree for 2/3/5GHz bands respectively. The transceiver ensures low EVM over the wide dynamic range due to highly linear RX and TX signal paths, and low integrated PLL phase noise characteristics.

A 2×2 MIMO multi-band RF transceiver and power amplifier for compact LTE small cell base station

We present a fully integrated 2×2 MIMO CMOS LTE RF transceiver along with multi-band InGaP/GaAs HBT power amplifiers for LTE-A small cell (femtocell) base stations. The transceiver features highly integrated LNAs and drive amplifiers with 24 individual RF I/O pins. The multi-band PAs achieves ACLR <-45dBc at 25dBm with PAE >38% at 33dBm by employing a third-order intermodulation distortion (IMD3) canceling techniques. The presented SiP composed of proposed radio and PAs shows plenty of margins in radio conformal test of femtocell base station using a commercial modem.