Shaowu Huang

Suppression of Cavity Resonant Edge Effects and PDN impedance using absorbing material

Cavity Resonant Edge Effects (CREE) in printed circuit boards (PCBs) and packages can cause severe power integrity (PI) and electromagnetic interference/compatibility (EMI/EMC) issues. Electromagnetic radiation from PCB edges are major sources of EMI/EMC problems in electronic devices. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and packages using power vias. CREE produces considerable level of noise along the edges of PCB and package power planes due to signal coupling between vias and reflection along PCB edges with transient currents. In this paper, we investigate an approach to minimize cavity resonant noise by placing absorbing material along the edges of a PCB board. The upper peak (anti-resonant) impedance of the power distribution network (PDN) is reduced significantly. In this paper the simulated example shows the absorbing material reduces the upper impedance peaks as much as to 8% comparing to the impedance peaks without absorption material. Conclusively, the results show that adding absorbing material along the PCB edges significantly improves the noise issues by suppressing CREE.

Novel Broadband Equalizer Optimization Technique for High-Speed Digital System Designs

In this paper, a novel broadband equalizer optimization technique is introduced for highspeed digital system designs. Through effectively compensating both conductor loss and dielectric loss, this technique provides a new solution to find optimal equalizer for high-speed signaling over printed circuit board (PCB) with continuous time linear equalizer (CTLE) as an application. The coefficients of CTLE are quickly identified through searching the minimum of the variation of total transfer functions over the low-mid frequency range. Channel simulations with different server interfaces of 12 Gbps and 25 Gbps are performed, respectively. Simulation results are presented to validate the technique.

Suppression of Couplings in High-Speed Interconnects Using Absorbing Materials

In this paper, we propose and investigate two novel applications of absorbing materials to suppress high-frequency couplings in high-speed interconnects. In the first application, absorbing materials are added to connector housing to reduce the noises caused by crosstalk and resonances. In the second application, a low-emission inductor is proposed by applying absorbing materials surrounding the body of an inductor. Full-wave simulations and measurements are performed to verify the proposed techniques. Results show absorbing materials significantly improve the performance of signal/power integrity and greatly reduce electromagnetic interference for high-speed digital system designs.

Stub Effect Mitigations Using Absorbing Materials

A new technology is developed for the mitigation of stub effects in high-speed interconnects. This technology substantially reduces the stub effects for high-speed signaling. It dampens reflected signals on stubs, thus reducing intersymbol interference and harmful coupling, and correcting timing jitter, all typically induced by the stubs reflected signals. This paper shows two applications for high-speed digital system designs, the mitigation of via stub effects and that of empty connector effects, respectively. However, it is notable that the present method is suitable for reflection suppression for arbitrary types of stubs to improve the signal integrity.

Rigorous one-port measurement method for the characterization of on-chip pad response

The paper presents a rigorous, one-port measurement technique for the characterization of on-chip pad response, particularly the pad capacitance (Cpad). By adding two independent (“short” and “match”, or two terminations with known impedance other than “open”) standards to the existing one-port method, the method eliminates the errors in the current vector network analyzer (VNA) method, while providing frequency-dependent data. This not only overcomes the fundamental restriction in conventional two-port measurement methods that are prohibitively complex, but also is better than existing one-port methods that are inaccurate due to lack of two independent measurements. Simulations and experiments are performed to validate the proposed method in the paper.

Improve electrical performance of interconnects using inkjet printing

In this paper, a technique is proposed to improve the electrical performance of high speed signaling through direct printing additional dielectric or other types of materials onto the PCB interconnect using inkjet printing. Inkjet printing is used to coat thin film or other structures onto the microstrip, via pad, pin field, or other structures on PCB. The electrical performance of interconnects can be adjusted and improved through such process. As an example, Inkjet printing can be used to increase the dielectric thickness of microstrip cover layer (soldermask), and thus to suppress the far end crosstalk and improve the insertion loss. This potentially is better than conventional PCB manufacturing techniques such as photo-lithography, which requires many process steps, which lead to higher cost and longer development time.

Probe with absorbing materials

In this paper through integrating absorbing materials onto a probe as terminators to eliminate the reflected noises on device under test (DUT), a novel on-probe termination technique is introduced for high frequency measurements. Absorbing material is suitable for on-probe termination, since there is no need of “ground” which is required in conventional resistive termination, and it also provides better flexibility in on-probe design. Measurement are performed to test the feasibility of proposed technique. Results show absorbing terminators can effectively terminate reflected signals and eliminate noises. The proposed technique provides innovative on-probe termination solution for cost reduction or/and feasibility improvement in high frequency measurements.

Novel de-embedding method with Look-Up Table for characterization of interconnects

A new de-embedding technique is introduced in this paper with pre-established Look-Up Table (LUT) for accurate characterization of high speed interconnects, particularly for printed circuit board (PCB). The method de-embeds the test fixture effects from the measurement or/and simulation results. It improves the accuracy and reduces the PCB layout area comparing to one line method. It reduces the PCB layout area and improves the measurement efficiency comparing to two line method.

Novel through hole absorber for suppression of power noise, crosstalk and EMI

In this paper, novel through hole/embedded absorbers based on absorbing materials are used to suppress the cavity resonant effects of power delivery networks (PDNs) in printed circuit boards (PCBs). The proposed technique can substantially reduce PDN impedances and EMI, and improves the signal and power integrity of interconnects for computer and electronic system designs. The embedded absorbers can be implemented by drilling through holes or/and arbitrarily shaped slots in the PCB or package, and then filling in the holes/slots with absorbing materials. As an example, full wave simulations are performed and results show that the proposed technique significantly reduces PDN impedances and radiated electric fields from PCB, though it is generic technique for mitigating other issues including crosstalk which are caused by PDN cavity resonant effects.

REDUCTION OF PCB PDN IMPEDANCE AND RADIATED EMISSIONS USING A HYBRID TECHNIQUE WITH ABSORBING MATERIALS AND DECOUPLING CAPACITORS

In this paper, we present an approach to reduce the cavity resonant edge effects in printed circuit boards (PCBs) and semiconductor packages. Power supply noise, in the form of fast changing currents (di/dt), traverses the power-return paths of PCBs and semiconductor packages using power vias. The cavity effects produce considerable level of noise along the edges of PCB and integrated circuit (IC) package power planes due to signal coupling between vias and reflection from PCB edges with transient currents. The cavity effects also amplify the electromagnetic radiation from PCB edges, which are major sources of EMI/EMC problems in electronic devices. By using absorbing material and decoupling capacitors (de-caps) on power distribution networks (PDNs), we observe considerable mitigation in impedance noise, signal noise and electromagnetic interference/compatibility (EMI/EMC) issues caused by the cavity effects. In particular, simulation results show notable reduction of upper peak (anti-resonant) impedance noise and reduction in radiated emissions by as much as 20 dB. This article presents a comparative case-study using various models (Section 3) and report on their effectiveness to reduce the cavity effects. The models are listed as (1) “Original” model, (2) “Absorbing material along the edge” model, (3) “MURATA based De-cap only” model and (4) “Absorbing material along the edge w/De-cap” model. The used capacitance ranges between 0.1 μF and 22 μF. The ESR and ESL range between 2mOhm–20 mOhm and 238 pH–368 pH, respectively. Conclusively, we learn by adding absorbing material along the PCB edges with a few decoupling capacitors. The PDN impedance noise is improved, and EMI issues in PCBs and semiconductor packages suppress the cavity effects.