Xiaoning Ye

Accurate characterization of PCB transmission lines for high speed interconnect

Accurate PCB transmission-line characterization can be challenging due to the effect of test fixtures and launching vias, etc. In this paper, VNA measurements with innovative de-embedding approaches, including those that utilize only one “2X-Thru” calibration standard are studied. The 2X-Thru de-embedding method is first shown to be correlated to existing TRL calibration method. Test boards built with varying lengths of transmission lines routed on different layers were then characterized with the new de-embedding method. Excellent de-embedded results are achieved for frequencies up to 30 GHz.

Analytical and numerical sensitivity analyses of fixtures de-embedding

De-embedding procedures are sensitive to manufacturing variations in test fixtures, as well as inaccuracies associated with the calibration and measurement process. Such sensitivities can propagate through de-embedding procedures, resulting in amplified errors. In this paper, analytical and numerical techniques are used to perform sensitivity studies on both simulation and measurement data, with respect to de-embedding.

A novel de-embedding method suitable for transmission-line measurement

A novel de-embedding method on transmission line device under testing (DUT) is introduced in this paper. The technique can be used as an alternative to classic calibration approaches, such as SOLT, TRL, LRM, or LRRM whenever the de-embedded structure is a transmission line. The method only requires two measurement patterns: a true through as test fixture and a total pattern with targeting DUT embedded in. With a quasi-symmetry requirement in test fixtures, it is also a good substitute for newly released two-pattern de-embedding methodologies which have rigid symmetric demanding in text fixtures design and manufactures.

Validating the transmission-line based material property extraction procedure including surface roughness for multilayer PCBs using simulations

Accurate frequency-dependent dielectric properties are important for accurate modeling of signal and power integrity problems. One method for extracting dielectric properties from fabricated multilayer printed circuit boards is based on the measured electrical property of fabricated transmission lines, denoted the “Root-omega” method. In this paper, the “Root-omega” method applied to the cases with smooth and rough conductors is validated using simulations. Potential errors in the procedure are discussed.

Improve electrical performance of interconnects using inkjet printing

In this paper, a technique is proposed to improve the electrical performance of high speed signaling through direct printing additional dielectric or other types of materials onto the PCB interconnect using inkjet printing. Inkjet printing is used to coat thin film or other structures onto the microstrip, via pad, pin field, or other structures on PCB. The electrical performance of interconnects can be adjusted and improved through such process. As an example, Inkjet printing can be used to increase the dielectric thickness of microstrip cover layer (soldermask), and thus to suppress the far end crosstalk and improve the insertion loss. This potentially is better than conventional PCB manufacturing techniques such as photo-lithography, which requires many process steps, which lead to higher cost and longer development time.

Probe with absorbing materials

In this paper through integrating absorbing materials onto a probe as terminators to eliminate the reflected noises on device under test (DUT), a novel on-probe termination technique is introduced for high frequency measurements. Absorbing material is suitable for on-probe termination, since there is no need of “ground” which is required in conventional resistive termination, and it also provides better flexibility in on-probe design. Measurement are performed to test the feasibility of proposed technique. Results show absorbing terminators can effectively terminate reflected signals and eliminate noises. The proposed technique provides innovative on-probe termination solution for cost reduction or/and feasibility improvement in high frequency measurements.

Via pattern design and optimization for differential signaling 25Gbps and above

Ground via design rules may need to be re-visited to support high-speed signaling for 25Gbps and above, according to our experience. In this paper, the study begins with some basic via patterns with different ground via placement to investigate loss, crosstalk, common mode, and electromagnetic field distribution to help understand the underlying physics. The benefit of joint anti-pad is also analyzed for signaling at 25Gbps and above. Impact of adjacent vias to the modeled via pair of interest is studied and it is found that the adjacent vias should be properly terminated and included in the modeling. Finally crosstalk study is performed for the given via patterns.

Dual-striplines design optimizations for minimum crosstalk

Dual-stripline is widely used in the computer systems to save printed circuit board (PCB) cost and achieve more compact form factor. Many design parameters can affect the overall performance of the dual-striplines. In this paper, the optimization of the dual-stripline design is discussed in detail, such as stackup selection, component breakout, etc. Theory analysis as well as Three-Dimensional full-wave modelling results of the inter-layer crosstalk for both single-ended and differential dual-stripline are presented to understand the inter-layer crosstalk. Measurement data from a test board is used to correlate the modeling result. An end-to-end simulation flow is proposed to precisely evaluate the overall crosstalk and full-link performance of a design with dual-stripline.

Signal integrity performance degradation due to temperature variation in systems with re-drivers

Re-drivers are widely used in extending the solution space in high speed applications. However, recent lab data shows that the ambient temperature variation can lead to ~40mV degradation of the eye height at the receiver side on single re-driver system. In this paper, the authors will share key learnings of thermal impact on systems with both single re-driver and cascaded re-drivers. From these cases, the eye height is greatly reduced when temperature increases. This variation is due to resistance shifting of the output buffer, while most re-driver models do not account for it. An effective approach is applied to fine tune the equalization settings in the cascaded re-driver system. The learnings, together with the proposed approach, can help designers to design a robust, high performance, and cost-effective high speed link with re-drivers such as SAS-3, SATA-3, PCIe and USB, etc.

Novel characterization technique with short and open standards

In this paper, through introducing the short and open standards and excluding the match (termination) standard, a technique is proposed to simplify the measurement of symmetric device under test (DUT). Because the short and open standards are usually easier to obtain than the match (termination) standard in terms of cost and/or feasibility, this technique provides more cost-effective and more flexible solution for characterization of symmetric systems and interconnects.