Berkehan Ciftcioglu

An intra-chip free-space optical interconnect

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect is a promising long term solution. However, while significant progress in optical signaling has been made in recent years, networking issues for on-chip optical interconnect still require much investigation. Taking the underlying optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of optical interconnects. In this paper, we propose and study the design of a fully distributed interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.

Nanospintronics Based on Magnetologic Gates

We present a seamless integration of spin-based memory and logic circuits. The building blocks are magnetologic gates based on a hybrid graphene/ferromagnet material system. We use network search engines as a technology demonstration vehicle and simulate a high-speed, small-area, and low-power spin-based circuit.

Injection-Locked Clocking: A New GHz Clock Distribution Scheme

We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injection-locked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18mum digital CMOS technology. It has four divide-by-2 ILOs at the leaves of a 3-section H-tree, generating 5GHz local clocks from the 10GHz input clock with 17% locking range and no phase noise degradation. Measured jitter of generated clocks is lower than that of the input signal. Two local clocks can be differentially deskewed up to 80ps relative to each other. The test chip consumes only 7.3mW excluding test-port buffers

3-D integrated heterogeneous intra-chip free-space optical interconnect

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

Integrated Silicon PIN Photodiodes Using Deep N-Well in a Standard 0.18-

This paper studies integrated silicon photodiodes (PDs) implemented in standard CMOS technologies. A new PIN PD structure utilizing deep n-well is presented, and compared with conventional vertical and lateral PIN PDs at 850-nm wavelength and different bias conditions. Prototype PDs were fabricated in a 0.18-mum standard CMOS technology, and their DC, impulse and frequency responses were characterized. A 70 times 70 mum2 PD with the new structure achieved a 3-dB bandwidth of 2.2 GHz in small signal at 5-V bias, whereas conventional lateral and vertical PIN PDs could only operate up to 0.94 GHz and 1.15 GHz, respectively. At 5-V bias, the impulse response of the new PD exhibited a full-width at half-maximum pulsewidth of 127 ps, versus 175 and 150 ps for the conventional lateral and vertical ones, respectively. At 15.5-V bias, the bandwidth of this new PD reached 3.13 GHz, with an impulse response pulsewidth of 102 ps. The responsivity of all prototype PDs was measured at approximately 0.14 A/W up to 10-V bias, which corresponded to a quantum efficiency of 20%. The responsivity of the new PD could be further increased to 0.4 A/W or 58% quantum efficiency, when operating in the avalanche region at 16.2-V bias.

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We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 m and 3 GHz. Simulations show 20- and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC configurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18- m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.

m CMOS Technology

This letter presents a new optical interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and -26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.

Injection-Locked Clocking: A Low-Power Clock Distribution Scheme for High-Performance Microprocessors

This paper presents a new photonic integrated circuit, namely optical pulse-train generator, which is developed based on the transfer matrix analysis of microrings and utilizes a time-interleaved architecture. This circuit can generate multiple optical pulses sequentially from a single trigger pulse, with the timing and amplitude of each pulse determined by circuit design. Hence it can be applied in optical arbitrary waveform generation and ultrafast electro-optic modulation. A four-tap prototype pulse-train generator design is demonstrated, and the challenge of distributed optical power combining is discussed. The design techniques presented in this paper will find use in other large scale photonic integrated circuit applications.

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

A new PIN photodiode (PD) structure with deep n-well (DNW) fabricated in an epitaxial substrate complementary metal-oxide-semiconductor (epi-CMOS) process is presented. The DNW buried inside the epitaxial layer intensifies the electric field deep inside the epi-layer significantly, and helps the electrons generated inside the epi-layer to drift faster to the cathode. Therefore, this new structure reduces the carrier transit time and enhances the PD bandwidth. A PD with an area of 70 times 70 mum2 fabricated in a 0.18-mum epi-CMOS achieves 3-dB bandwidth of 3.1 GHz in the small signal and 2.6 GHz in the large signal, both with a 15-V bias voltage and 850-nm optical illumination. The responsivity is measured 0.14 A/W, corresponding to a quantum efficiency of 20%, at low bias. The responsivity increases to 0.4 A/W or 58% quantum efficiency at 16.2-V bias in the avalanche mode.

Microring-based optical pulse-train generator

Injection-locked clocking (ILC) has been proposed previously to improve the skew and jitter performance while reducing the power consumption in multi-gigahertz clock distribution networks. This paper presents a new design of the injection-locked oscillator (ILO) suitable for ILC applications. It uses a transformer to generate differential signals and then directly inject them into the ILO core. It also incorporates a switched-capacitor array for frequency tuning and hence digital deskew in ILC. A 4 GHz test chip was designed and fabricated in a 0.18 mum standard digital CMOS. It consists of four ILOs driven by a balanced H-tree. Each ILO consumes less than 1 mW from a 1 V power supply. 5-bit digital deskew achieves 55 ps delay tuning range and 1.8 ps resolution. Measurement shows that only 30 fs cycle-to-cycle jitter degradation was introduced and no phase noise degradation at frequency offset up to 600 kHz.