Jianyun Hu

An intra-chip free-space optical interconnect

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect is a promising long term solution. However, while significant progress in optical signaling has been made in recent years, networking issues for on-chip optical interconnect still require much investigation. Taking the underlying optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of optical interconnects. In this paper, we propose and study the design of a fully distributed interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.

3-D integrated heterogeneous intra-chip free-space optical interconnect

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

A case for globally shared-medium on-chip interconnect

As microprocessor chips integrate a growing number of cores, the issue of interconnection becomes more important for overall system performance and efficiency. Compared to traditional distributed shared-memory architecture, chip-multiprocessors offer a different set of design constraints and opportunities. As a result, a conventional packet-relay multiprocessor interconnect architecture is a valid, but not necessarily optimal, design point. For example, the advantage of off-the-shelf interconnect and the in-field scalability of the interconnect are less important in a chip-multiprocessor. On the other hand, even with worsening wire delays,packet switching represents a non-trivial component of overall latency. In this paper, we show that with straight forward optimizations, the traffic between different cores can be kept relatively low. This in turn allows simple shared-medium interconnects to be built using communication circuits driving transmission lines. This architecture offers extremely low latencies and can support a large number of cores without the need for packet switching, eliminating costly routers.

An Ultra-Wideband Resistive-Feedback Low-Noise Amplifier with Noise Cancellation in 0.18μm Digital CMOS

We present a wideband resistive feedback CMOS low-noise amplifier (LNA) with noise cancellation technique for ultra-wideband applications. The LNA achieves a 3-dB bandwidth of 0.7-6.5 GHz, power gain of 12.5 dB, and noise figure of 3.5-4.2 dB within the 3-dB bandwidth. The input matching is better than -11 dB from 0.7 to 12 GHz. The IIP3 is measured -5 dBm at 5 GHz. It is implemented in a 0.18 mum standard digital CMOS technology, occupies an area of 0.78 mmtimes0.68 mm, and consumes 11.1 mW from a 1.8 V supply.

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

This letter presents a new optical interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and -26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.

Enhancing effective throughput for transmission line-based bus

Main-stream general-purpose microprocessors require a collection of high-performance interconnects to supply the necessary data movement. The trend of continued increase in core count has prompted designs of packet-switched network as a scalable solution for future-generation chips. However, the cost of scalability can be significant and especially hard to justify for smaller-scale chips. In contrast, a circuit-switched bus using transmission lines and corresponding circuits offers lower latencies and much lower energy costs for smaller-scale chips, making it a better choice than a full-blown network-on-chip (NoC) architecture. However, shared-medium designs are perceived as only a niche solution for small- to medium-scale chips. In this paper, we show that there are many low-cost mechanisms to enhance the effective throughput of a bus architecture. When a handful of highly cost-effective techniques are applied, the performance advantage of even the most idealistically configured NoCs becomes vanishingly small. We find transmission line-based buses to be a more compelling interconnect even for large-scale chip-multiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect.

A design space exploration of transmission-line links for on-chip interconnect

With increasing core count, chip multiprocessors (CMP) require a high-performance interconnect fabric that is energy-efficient Well-engineered transmission line-based communication systems offer an attractive solution, especially for CMPs with a moderate number of cores. While transmission lines have been used in a wide variety of purposes, there lack comprehensive studies to guide architects to navigate the circuit and physical design space to make proper architecture-level analyses and tradeoffs. This paper makes a first-ste effort in exploring part of the design space. Using detailed simulation-based analysis, we show that a shared-medium fabric based on transmission line can offer better performance and a much better energy profil than a conventional mesh interconnect.

A 2.5 Gpulse/s, 25 pJ/pulse, 0.18μm CMOS Impulse Radio UWB Transmitter Based on Dual-Polarity Distributed Waveform Generator

In this paper, we present a fully-integrated impulse radio UWB transmitter based on a newly-developed ultrafast pulse circuit technique, distributed waveform generator (DWG). A DWG time-interleaves multiple digital pulse generators, and then combines all generated pulses using a wideband on-chip transmis- sion line. A DWG is low power and fully reconfigurable compared to other UWB pulse generation and shaping solutions. It also facilitates the implementation of digital modulation schemes such as on-off keying (OOK) and pulse position modulation (PPM) in the transmitter. A chip prototype with a 10-tap, 10 GS/s dual-polarity DWG was designed and implemented in 0.18µm standard digital CMOS. The transmitters pulse rate can be varied from 16 MHz to 2.5 GHz with an energy efficiency of 25 pJ/pulse. The transmitted pulses with OOK and PPM modulation are successfully demonstrated using 32 Mb/s PRBS data.

Energy efficient, reconfigurable, distributed pulse generation and detection in UWB impulse radios

Ultrafast pulse generation and detection are pivotal functions in ultra-wideband (UWB) impulse radios. This paper shows that digitally-assisted distributed circuit techniques provide an energy-efficient, reconfigurable solution for both functions, as demonstrated in two new circuits: a pulse generator that can generate reconfigurable pulse waveforms with sub-nanosecond time resolution, and a multi-GHz analog correlator that incorporates reconfigurable local template pulse generation. A UWB impulse radio was developed based on these new circuits with chip prototypes implemented in 0.18-µm standard digital CMOS. It was characterized using UWB antennas, and achieved an energy efficiency of 25-pJ/pulse for the transmitter and 190-pJ/pulse for the receiver at 250 MHz pulse rate in the measurement.

A 0.17-nJ/pulse IR-UWB receiver based on distributed pulse correlator in 0.18-µm digital CMOS

This paper presents a low power impulse-radio ultra-wideband (IR-UWB) receiver based on a reconfigurable, high speed analog correlator called distributed pulse correlator (DPC). The DPC incorporates built-in local template pulse generation, and hence significantly reduces the power consumption and circuit complexity of the analog correlation receiver. A chip prototype of the IR-UWB receiver was implemented in 0.18-µm standard digital CMOS, and achieved an energy efficiency of 0.17-nJ/pulse at 250-MHz pulse rate in the measurement.