Ioannis Savidis

Closed-Form Expressions of 3-D Via Resistance, Inductance, and Capacitance

Closed-form expressions of the resistance, capacitance, and inductance for interplane 3-D vias are presented in this paper. The closed-form expressions account for the 3-D via length, diameter, dielectric thickness, and spacing to ground. A 3-D numerical simulation is used to extract electromagnetic solutions of the resistance, capacitance, and inductance for comparison with the closed-form expressions, revealing good agreement between simulation and the physical models. The maximum error for the resistance, capacitance, and inductance is less than 8%.

Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits

The integration of chips in the third dimension has been explored to address various physical and system level limitations currently undermining chip performance. In this paper, we present a comprehensive analysis of the electrical properties of through silicon vias and microconnects with an emphasis on single via characteristics as well as inter-TSV capacitive and inductive coupling in the presence of either a neighboring ground tap or a grounded substrate back plane. We also analyze the impact of technology scaling on TSV electrical parasitics, and investigate the power and delay trend in 3-D interstratum IO drivers with those of global wire in 2-D circuits over various technology nodes. We estimate the global wire length necessary to produce an equivalent 3-D IO delay, a metric useful in early stage design tools for 3D floorplanning that considers the electrical characteristics of 3D connections with TSVs and microconnects.

An intra-chip free-space optical interconnect

Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless scaling, if uncompensated, degrades the performance and signal integrity of on-chip metal interconnects. These systems have therefore become increasingly communications-limited. The communications-centric nature of future high performance computing devices demands a fundamental change in intra- and inter-chip interconnect technologies. Optical interconnect is a promising long term solution. However, while significant progress in optical signaling has been made in recent years, networking issues for on-chip optical interconnect still require much investigation. Taking the underlying optical signaling systems as a drop-in replacement for conventional electrical signaling while maintaining conventional packet-switching architectures is unlikely to realize the full potential of optical interconnects. In this paper, we propose and study the design of a fully distributed interconnect architecture based on free-space optics. The architecture leverages a suite of newly-developed or emerging devices, circuits, and optics technologies. The interconnect avoids packet relay altogether, offers an ultra-low transmission latency and scalable bandwidth, and provides fresh opportunities for coherency substrate designs and optimizations.

Clock distribution networks for 3-D ictegrated Circuits

Three-dimensional (3D) integration is an important technology that addresses fundamental limitations of on-chip interconnects. Several design issues related to 3D circuits, such as multi-plane synchronization, however, need to be addressed. A comparison of three 3D clock distribution network topologies is presented in this paper. Experimental results of a 3D test circuit manufactured by the MIT Lincoln Laboratories are also described. Successful operation of the 3D test circuit at 1.4 GHz is demonstrated. Clock skew and power dissipation measurements for the different clock topologies are also provided.

Electrical modeling and characterization of 3-D vias

Electrical characterization of the resistance, capacitance, and inductance of inter-plane 3-D vias is presented in this paper. Both capacitive and inductive coupling between multiple 3-D vias is described as a function of the separation distance and plane location. The effects of placing a third shield via between two signal vias is investigated as a means to limit the capacitive coupling. The location of the return path is examined to determine the best placement of a 3-D via to reduce the overall loop inductance. Based on the extracted resistance, capacitance, and inductance, the L/R time constant is shown to be much larger than the RC time constant, demonstrating that the 3-D via structure investigated in this paper is inductively limited rather than capacitively limited.

3-D integrated heterogeneous intra-chip free-space optical interconnect

This paper presents the first chip-scale demonstration of an intra-chip free-space optical interconnect (FSOI) we recently proposed. This interconnect system provides point-to-point free-space optical links between any two communication nodes, and hence constructs an all-to-all intra-chip communication fabric, which can be extended for inter-chip communications as well. Unlike electrical and other waveguide-based optical interconnects, FSOI exhibits low latency, high energy efficiency, and large bandwidth density, and hence can significantly improve the performance of future many-core chips. In this paper, we evaluate the performance of the proposed FSOI interconnect, and compare it to a waveguide-based optical interconnect with wavelength division multiplexing (WDM). It shows that the FSOI system can achieve significantly lower loss and higher energy efficiency than the WDM system, even with optimistic assumptions for the latter. A 1×1-cm2 chip prototype is fabricated on a germanium substrate with integrated photodetectors. Commercial 850-nm GaAs vertical-cavity-surface-emitting-lasers (VCSELs) and fabricated fused silica microlenses are 3-D integrated on top of the substrate. At 1.4-cm distance, the measured optical transmission loss is 5 dB, the crosstalk is less than -20 dB, and the electrical-to-electrical bandwidth is 3.3 GHz. The latter is mainly limited by the 5-GHz VCSEL.

Clock Distribution Networks in 3-D Integrated Systems

3-D integration is an important technology that addresses fundamental limitations in on-chip interconnects. Several design issues related to 3-D circuits, such as multiplane synchronization, however, need to be addressed. A comparison of three 3-D clock distribution network topologies is presented in this paper. Good agreement is shown between the modeled and experimental results of a 3-D test circuit composed of three device planes. Successful operation of the 3-D test circuit at 1.4 GHz is demonstrated. Clock skew, clock delay, signal slew, and power dissipation measurements for the different clock topologies are also provided. The measurements suggest that each topology provides certain advantages and disadvantages in terms of different performance criteria. The proper choice, consequently, of a clock distribution network is not dictated by a single design objective but rather by the overall 3-D system design requirements including availability of resources and number of bonded planes.

Power Noise in TSV-Based 3-D Integrated Circuits

A three-dimensional (3-D) test circuit examining power grid noise in a 3-D integrated stack has been designed, fabricated, and tested. Fabrication and vertical bonding were performed by MIT Lincoln Laboratory for a 150 nm, three metal layer SOI process. Three wafers are vertically bonded to form a 3-D stack. Noise analysis of three power delivery topologies is described. Calibration circuits for a source follower sense circuit compare the different power delivery topologies as well as the separate 3-D stacked circuits. The effect of the through silicon via (TSV) density on the noise profile of a 3-D power delivery network is experimentally described. A comparison of the peak noise for each topology with and without board level decoupling capacitors, and resonant behavior is provided, and suggestions for enhancing the design of a 3-D power delivery network are offered.

A 3-D Integrated Intrachip Free-Space Optical Interconnect for Many-Core Chips

This letter presents a new optical interconnect system for intrachip communications based on free-space optics. It provides all-to-all direct communications using dedicated lasers and photodetectors, hence avoiding packet switching while offering ultra-low latency and scalable bandwidth. A technology demonstration prototype is built on a circuit board using fabricated germanium photodetectors, micro-lenses, commercial vertical-cavity surface-emitting lasers, and micro-mirrors. Transmission loss in an optical link of 10-mm distance and crosstalk between two adjacent links are measured as 5 and -26 dB, respectively. The measured small-signal bandwidth of the link is 10 GHz.

ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling

Heterogeneous architectures have emerged as a promising solution to enhance energy-efficiency by allowing each application to run on a core that matches resource needs more closely than a one-size-fits-all core. In this paper, an ElasticCore platform is described where core resources along with the operating voltage and frequency settings are scaled to match the application behavior at run-time. Furthermore, a linear regression model for power and performance prediction is used to guide the scaling of the core size and the operating voltage and frequency to maximize efficiency. Circuit considerations that further optimize the power efficiency of ElasticCore are also considered. Specifically, the efficiency of both off-chip and on-chip voltage regulators is analyzed for the heterogeneous architecture where the required load current changes dynamically at run-time. A distributed on-chip voltage regulator topology is proposed to accommodate the heterogeneous nature of the ElasticCore. The results indicate that ElasticCore on average achieves close to a 96% efficiency as compared to an architecture implementing the Oracle predictor where the application behavior is perfectly matched at run-time. Moreover, the proposed architecture is 30% more energy-efficient as compared to the BigLitte architecture.