Bernard Mark Tenbroek

Single-Chip Tri-Band WCDMA/HSDPA Transceiver without External SAW Filters and with Integrated TX Power Control

With growing WCDMA adoption there is a strong demand to reduce the cost of WCDMA terminals. Contributing to the relatively high WCDMA terminal cost is the low integration of todays WCDMA radios. Since WCDMA is an FDD system the transmitter and receiver are on simultaneously. A duplexer is used to isolate the receiver from the transmit signal but the isolation of small low-cost duplexers is limited, with a guaranteed isolation at the TX frequency of not more than 52dB. For a Class-3 terminal with 2dB TX path loss due to duplexer and switch, the power at the PA output is +26dBm and the receiver will see a TX leakage of up to -26dBm. Todays state-of- the-art WCDMA transceivers deal with the TX blocking problem by using an external TX SAW filter to eliminate TX noise in the RX band and an external LNA and RX SAW filter to achieve sufficient RX linearity. A typical tri-band transceiver requires 6 SAW filters and 3 LNAs. The tri-band WCDMA transceiver presented here eliminates all external SAW filters and LNAs and achieves excellent performance with standard low-cost duplexers.

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included. Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

A multibit /spl Sigma//spl Delta/ modulator in floating-body SOS/SOI CMOS for extreme radiation environments

This paper presents the design of an experimental first-order /spl Sigma//spl Delta/ modulator with 4-bit internal quantization, fabricated in a 1.5-/spl mu/m space-qualified radiation-hard partially depleted silicon-on-sapphire (SOS) digital CMOS process. This converter architecture has been chosen partly to allow investigation into the design of a range of common analog functions with two key issues in mind: one of technology and one environmental. First, both the architecture and the circuit design are optimized using a variety of unconventional techniques to account for the influence of extreme bias-dependent, radiation-induced threshold-voltage shifts of up to 1 V, as well as poor 1/f device noise. Second, the circuitry is specially adapted to accommodate the floating-body behavior of this type of process, wherein drain conductance varies considerably with drain bias and frequency. The design techniques are directly applicable to very large-scale-integration silicon-on-insulator (SOI) design, where similar device physics are encountered. Notwithstanding the severe constraints on the design, the fabricated circuit provides 9.7 bits of dynamic range in a 63-kHz signal bandwidth, only degrading to 9.1 bits after 23 Mrad(Si) of total dose /spl gamma/ radiation.

A receiver for WCDMA/EDGE mobile phones with inductorless front-end in 65nm CMOS

The spectrum allocated for the operation of cellular services is country dependent and fragmented in several frequency bands [1]. Mobile phones, to be usable globally, are therefore required to support many bands. The lack of suitable tuneable pre-selection filters and duplexers mandates the use of a large number of low-noise amplifiers (LNAs) in the receiver section of the transceiver. Minimization of the area occupied by the LNAs is therefore important. Virtually every transceiver for mobile phone applications published to date makes use of LNAs employing on-chip [3,5] or on-passivation [4] spiral inductors. Spiral inductors are large and do not scale with technology, leading to an increasing relative cost of the receiver front-end with newer technology nodes. Post-passivation and SiP technologies also add noticeably to the costs. In this paper we present the first receiver employing no on-chip or above-passivation spiral inductors on the receive signal path and with a linearity and noise performance suitable for WCDMA/EDGE applications. The eight channel direct-conversion receiver is part of a multimode transceiver requiring neither RX nor TX interstage SAW filters for FDD 3G operation. A block diagram of the receiver is shown in Fig. 21.4.1.

A Low-Current Digitally Predistorted Direct-Conversion Transmitter With 25% Duty-Cycle Passive Mixer

A low-current direct-conversion transmitter (TX) is obtained by combining an efficient single-balanced 25% duty-cycle passive mixer with a low-bias single-ended driver. The nonlinearity of such architecture is aggravated by strong harmonics at the mixer output folding down to the fundamental frequency due to driver nonlinearity. To address this, a baseband mathematical model of the passive mixer plus nonlinear driver is derived. Then, based on this model, a novel digital-predistortion approach is disclosed. Implemented in 40-nm CMOS, the modulator and driver combined consume 45 mW when delivering a +3-dBm Release 99 WCDMA signal with 0.9% error vector magnitude (EVM) and -59-dBc adjacent-channel leakage power ratio (ACLR). In long-term evolution (LTE) mode, the TX delivers +0-dBm 10-MHz LTE 16QAM with -53-dBc ACLR and 1.2% EVM.

24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B 1dB for SAW-less LTE radio

LTE-advanced wireless receivers require high-linearity up-front filtering to prevent corruption of the in-band signals by strong out-of-band (OOB) signals and self-interference from the transmitter. SAW duplexer filters are generally used for this purpose, but supporting the plethora of existing and new bands becomes troublesome with separate filters for each band. In this paper we explore the possibility of combining an isolator with on-chip filtering. However, even with 15dB isolation, the on-chip filter needs to deal with up to +10dBm TX leakage and −15dBm OOB blocking, which requires an extremely high IIP3 around +50dBm and IIP2 around +90dBm. Recently inductorless tunable N-path-filter-based receivers achieved >10dBm compression point and good IIP3 of 20 to 30dBm. In order to further improve the receiver linearity to approach the extremely high IIP3 requirement for a SAW-less receiver, a high-linearity N-path bandpass/notch filter topology and receiver architecture are proposed in this paper.

A low-current digitally predistorted 3G-4G transmitter in 40nm CMOS

To create a wide-band transmit path with high current efficiency a single-balanced passive modulator is combined with a class-B single-ended resonant driver. The linearity of such configuration is limited by a strong 3rd harmonic response of the modulator combined with a strong third-order intermodulation in the driver. A novel digital predistortion approach is presented to enable good linearity under these highly non-linear conditions. Implemented in 40nm CMOS, the modulator and driver combined consume only 45mW to deliver a +3dBm Release 99 WCDMA signal with 1.1% EVM, -54dBc ACLR and -160dBc/Hz noise in the RX band. The ACLR remains below -50dBc over temperature, frequency and TX-power without adjustment of the predistortion coefficients. The transmitter delivers +0dBm 10MHz LTE with -51dBc ACLR.

A mixer-first receiver with enhanced selectivity by capacitive positive feedback achieving +39dBm IIP3 and <3dB noise figure for SAW-less LTE Radio

A mixer-first receiver enhanced with capacitive positive feedback is proposed to obtain a steeper filter roll-off and enhanced linearity, while keeping low noise figure. It covers all sub-6GHz cellular bands and achieves a high IIP3 of +39dBm and blocker 1dB gain compression point of +12dBm for a blocker frequency-offset of 80MHz at fLO=2GHz. The NF ranges from 2.4dB at fLO=1GHz to 5.4dB at fLO=6GHz. The chip has been fabricated in Globalfoundries 45nm SOI technology on a high resistivity substrate.

13.1 A fully integrated multimode front-end module for GSM/EDGE/TD-SCDMA/TD-LTE applications using a Class-F CMOS power amplifier

The RF front-end complexity in 4G multimode multiband cellular radios has increased dramatically, requiring integration of PAs, filters and switches in a single module to reduce the RF footprint. This paper presents a fully integrated multimode TDD transmit front-end module (TXM) supporting GSM/EDGE/TD-SCDMA/TD-LTE in multiple bands. The TXM is implemented with three die on a 2-layer laminate LGA module (Figs. 13.1.1 and 13.1.7). Two multimode multiband power amplifier paths (LB/HB) are implemented in a 0.153µm 1P6M CMOS process, followed by power combiners and harmonic filters in a 0.18µm 3M2V IPD die and finally an SP10T antenna switch in a 0.18µm 1P3M SOI process. The Si substrate of good thermal conductivity dissipates the heat generated by PA transistors to the laminated substrate, which solder mask opened and lots of ground vias are deployed underneath the die to effectively conduct the heat out of the package.

Enhanced-Selectivity High-Linearity Low-Noise Mixer-First Receiver With Complex Pole Pair Due to Capacitive Positive Feedback

A mixer-first receiver (RX) with enhanced selectivity and high dynamic range is proposed, targeting to remove surface acoustic-wave-filters in mobile phones and cover all frequency bands up to 6 GHz. Capacitive negative feedback across the baseband (BB) amplifier serves as a blocker bypassing path, while an extra capacitive positive feedback path offers further blocker rejection. This combination of feedback paths synthesizes a complex pole pair at the input of the BB amplifier, which is upconverted to the RF port to obtain steeper RF bandpass filter roll-off and reduced distortion. This paper explains the circuit principle and analyzes RX performance. A prototype chip fabricated in 45-nm partially depleted silicon on insulator (SOI) technology achieves high out-of-band linearity (input-referred third-order intercept point (IIP3) = 39 dBm and input-referred second-order intercept point (IIP2) = 88 dB) combined with sub-3-dB noise figure. Desensitization due to a 0-dBm blocker is only 2.2 dB at 1.4 GHz.