Hsiang-Hui Chang

A wide-range delay-locked loop with a fixed latency of one clock cycle

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.

A spread-spectrum clock generator with triangular modulation

In this paper, a spread-spectrum clock generator (SSCG) with triangular modulation is presented. Only a divider and a programmable charge pump are added into a conventional clock generator to accomplish the spread-spectrum function. The proposed circuit has been fabricated in a 0.35-/spl mu/m CMOS single-poly quadruple-metal process. The proposed SSCG can generate clocks of 66, 133, and 266 MHz with center spread ratios of 0.5%, 1%, 1.5%, 2%, and 2.5%. Experimental results confirm the theoretical analyses.

A wide-range and fast-locking all-digital cycle-controlled delay-locked loop

An all-digital cycle-controlled delay-locked loop (DLL) is presented to achieve wide range operation, fast lock and process immunity. Utilizing the cycle-controlled delay unit, the proposed DLL reuses the delay units to enlarge the operating frequency range rather than cascade a huge number of delay units. Adopting binary search scheme, the two-step successive-approximation-register (SAR) controller ensures the proposed DLL to lock the input clock within 32 clock cycles regardless of input frequencies. The DLL operates in open-loop fashion once lock occurs in order to achieve low jitter operation with small area and low power dissipation. Since the DLL will not track temperature or supply variations once it is in lock, it is best suited for burst mode operation. Given a supplied reference input with 50% duty cycle, the DLL generates an output clock with the duty cycle of nearly 50% over the entire operating frequency range. Fabricated in a 0.18-/spl mu/m CMOS one-poly six-metal (1P6M) technology, the experimental prototype exhibits a wide locking range from 2 to 700 MHz while consuming a maximum power of 23 mW. When the operating frequency is 700 MHz, the measured peak-to-peak jitter and rms jitter is 17.6 ps and 2.0 ps, respectively.

A 0.7-2-GHz self-calibrated multiphase delay-locked loop

A 0.7-2-GHz precise multiphase delay-locked loop (DLL) using a digital calibration circuit is presented. Incorporating with the proposed digital calibration circuit, the mismatch-induced timing error among multiphase clocks in the proposed DLL can be self-calibrated. When the calibration procedure is finished, the digital calibration circuit can be turned off automatically to save power dissipations and reduce noise generations. A start controlled circuit is proposed to enlarge the operating frequency range of the DLL. Both the start-controlled circuit and the calibration circuit require an external reset signal to ensure the correctness of the calibration after temperature,operating frequency, and power supply voltage are settled. This DLL with the digital calibration circuit has been fabricated in a 0.18-/spl mu/m CMOS process. The measured results show the DLL exhibits a lock range of 0.7-2 GHz while the peak-to-peak jitter and rms jitter is 18.9ps and 2.5 ps at 2 GHz, respectively. When the calibration procedure is completed and the DLL operates at 1 GHz, the maximum mismatch-induced timing error among multiphase clocks is reduced from 20.4 ps (7.34 degree) to 3.5 ps (1.26 degree).

A low-jitter and precise multiphase delay-locked loop using shifted averaging VCDL

The DLL, in 0.35/spl mu/m CMOS, uses the shifted averaging VCDL to reduce the mismatch-induced timing error among the delay stages without extra hardware. The DLL can generate precise multiphase outputs with improved duty cycle, reduced skew errors, and lowered jitter. Compared with a conventional DLL, this design improves the peak-to-peak jitter by a factor of 1.4 at 150MHz.

A fast locking and low jitter delay-locked loop using DHDL

A fast-locking and low-jitter delay-locked loop (DLL) using the digital-controlled half-replica delay line (DHDL) is presented. The DHDL can provide stable bias voltage for the charge-pump circuit to achieve low-jitter performances; meanwhile, the property of bandwidth tracking can still be preserved. It can also provide a larger pumping current to reduce the lock time in the initialization state and provide a smaller current to improve jitter performance in the locked state. For comparisons, both the proposed DLL and the self-biased DLL have been fabricated in a 0.35-/spl mu/m one-poly four-metal CMOS process. From the measurement results, the proposed DLL has a shorter lock time and a better jitter performance than the self-biased DLL. The root-mean-squared jitter and peak-to-peak jitter are less than 4.2 and 30 ps, respectively, occurring at 75 MHz, over an operating frequency range of 50-150 MHz.

A shifted-averaging VCO with precise multiphase outputs and low jitter operation

A shifted-averaging VCO with precise multiphase outputs and low-jitter operation is presented in this paper. With the proposed shifted-averaging technique, the VCO could relax the phase errors and jitters caused by the mismatches among the active devices. Both the conventional and the proposed VCOs have been fabricated at the same die in a CMOS 0.35/spl mu/m 1P4M process. Compared to the conventional VCO, the proposed one could reduce the static phase errors among dell stages and improve jitters by a factor of 1.38.

A 0.8 V switched-opamp bandpass /spl Delta//spl Sigma/ modulator using a two-path architecture

In this paper, a very low-voltage fourth-order bandpass delta-sigma modulator with a two-path architecture is presented. Using the modified switched opamp technique enables the modulator to operate at only 0.8 V supply voltage without any voltage multiplier or bootstrapping switch. Realized in a 0.25 /spl mu/m 1P5M standard CMOS process, the prototype modulator exhibits a signal-to-noise-plus-distortion ratio (SNDR) of 60.6 db and a dynamic range (DR) of 68 db in a 30 kHz signal bandwidth centered at 1.25 MHz while consuming 2.5 mW and occupying an active area of 2.11 mm/sup 2/.

Low jitter Butterworth delay-locked loops

The low jitter Butterworth delay-locked loops (DLLs) are presented in this paper. The proposed Butterworth DLLs can suppress both the jitters generated by the input noise and the voltage-controlled delay line (VCDL) noise without stability considerations. Theoretically, the proposed Butterworth 2/sup nd/-order DLL and 3/sup rd/-order one could reduce the rms jitter due to the VCDL by a factor of /spl radic/2 and 2, respectively. In addition, a technique called dynamic bandwidth-adjusting scheme (DBAS) is adopted to shorten the lock time without compromising the jitter performance. The conventional DLL and the proposed ones are simultaneously fabricated at the same die in a CMOS 0.35-um one-poly four-metal process. Compared with the conventional DLL, the measured rms jitters of the proposed DLLs can be improved by a factor of 1.40 and 1.95, respectively, with an input frequency of 125 MHz. The maximum power consumption of the proposed DLLs is 32 mW.

A 6 MHz-130 MHz DLL with a fixed latency of one clock cycle delay

In this paper, a wide range delay-locked loop (DLL) with a fixed latency of one clock cycle is proposed. Using the phase selection circuit and the start-controlled circuit enlarges the operating frequency range of this DLL and eliminates the harmonic locking problems. The operating frequency range of the DLL can be from 1/T/sub Dmin/ to 1/(N/spl times/T/sub Dmax/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line theoretically. Fabricated in a 0.35 /spl mu/m 1P3M standard CMOS process, the DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz. The measurement results show that the operating frequency range is from 6 MHz to 130 MHz and the latency is just one clock cycle. From the entire operating frequency range, the maximum r.m.s. jitter would not exceed 25 ps.