Bernd Wuppermann

A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS

A 20 GS/s 8-bit ADC achieves a bandwidth of 6 GHz in 0.18 /spl mu/m CMOS. The implementation uses 80 time-interleaved current-mode pipeline sub-ADCs and stores data at 20 GB/s into a 1 MB on-chip memory. The ADC is packaged with a BiCMOS input buffer chip in a 438-ball BGA, and total power consumption is 10 W.

A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction

Metastable events in ADC comparators cause large errors that cannot be tolerated in test and measurement applications that record data over extended time intervals. This work utilizes BiCMOS technology to provide high dynamic range analog-to-digital conversion at 2.5GS/s with a metastable error rate of less than one error per year and better than 78dB SFDR over a 1GHz BW.

Architectures and Issues for Gigasample/second ADCs

Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is taking over in this former bastion of bipolar technology. We describe the issues common to all architectures: bandwidth, power, I/O, data storage, and cost. We examine these issues in detail for the time-interleaved approach as exemplified by two 8bit ADCs operating at 4 GSa/s and 20 GSa/s, implemented in CMOS.

An 8.2 to 20.1 GHz LC PLL with Sub-100 fs Jitter in 0.13 µm SiGe BICMOS

A dual-path PLL comprising two LC VCOs covers a tuning range from 8.2 to 20.1 GHz. Able to operate with a wide range of feedback-divider ratios (N), the PLL provides a total jitter of 65.3 fsrms when N=2 and 206.1 fsrms when N=16. In addition, the PLL achieves loop bandwidths up to 100 MHz which enables it to be used as a clean-up PLL at the receiver. In order to provide low jitter and low reference spurs for a wide range of reference frequencies, a novel architecture that uses switched multi-pole spur-reduction filters with dedicated phase detectors is introduced. The spur levels at the output are -55 dBc and -62 dBc when N=2 and N=16, respectively. Implemented in a 0.13 μm SiGe BiCMOS process, the 1.31 mm2 PLL dissipates a total of 302 mW from 1.2 V and 2.5 V supplies.

16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving −58dBFS noise and 4GHz bandwidth in 28nm CMOS

This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, Cbridge. Cbridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2Vppd full-scale range when a 1V reference is used.