Kenneth D. Poulton

A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS

A 20 GS/s 8-bit ADC achieves a bandwidth of 6 GHz in 0.18 /spl mu/m CMOS. The implementation uses 80 time-interleaved current-mode pipeline sub-ADCs and stores data at 20 GB/s into a 1 MB on-chip memory. The ADC is packaged with a BiCMOS input buffer chip in a 438-ball BGA, and total power consumption is 10 W.

A 1.2GS/s 15b DAC for precision signal generation

A 1.2GS/s 15b DAC achieves untrimmed SFDR of -70dBc to f/sub s//4 and -63dBc to Nyquist (with 10dB better results at 500MS/s). A per-element resampling scheme and dynamic element matching achieve DNL of 2LSB. In RZ output mode, ACPR for a 20MHz band at 900MHz is 69dB. The chip uses 40GHz-f/sub T/ NPN and is implemented in 0.35 /spl mu/m CMOS.