Robert M. R. Neff
Agilent Technologies
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Featured researches published by Robert M. R. Neff.
international solid-state circuits conference | 2003
Kenneth D. Poulton; Robert M. R. Neff; Brian D. Setterberg; Bernd Wuppermann; Tom Kopley; R. Jewett; J. Pernillo; C. Tan; A. Montijo
A 20 GS/s 8-bit ADC achieves a bandwidth of 6 GHz in 0.18 /spl mu/m CMOS. The implementation uses 80 time-interleaved current-mode pipeline sub-ADCs and stores data at 20 GB/s into a 1 MB on-chip memory. The ADC is packaged with a BiCMOS input buffer chip in a 438-ball BGA, and total power consumption is 10 W.
Archive | 2007
Ken Poulton; Robert M. R. Neff; Brian D. Setterberg; Bernd Wuppermann; Tom Kopley
Architectures for ADCs at 1 Gigasample/second (1 GSa/s) and beyond now include flash, folding and interpolating as well as the time interleaving of slower unit converters such as pipeline and even successive approximation ADCs. In addition, CMOS is taking over in this former bastion of bipolar technology. We describe the issues common to all architectures: bandwidth, power, I/O, data storage, and cost. We examine these issues in detail for the time-interleaved approach as exemplified by two 8bit ADCs operating at 4 GSa/s and 20 GSa/s, implemented in CMOS.
international solid-state circuits conference | 2017
John Keane; Nathaniel J. Guilar; Dusan Stepanovic; Bernd Wuppermann; Charles Wu; Cheongyuen W. Tsang; Robert M. R. Neff; Ken Nishimura
This paper describes an 8GS/s 16-way time-interleaved ADC for a test and measurement application. Each ADC slice is a 1b/cycle, synchronous SAR operating at 500MS/s. The ADC slice schematic is shown in Fig. 16.5.1. The input is sampled using a thick-oxide NFET driven by a 1.9V buffer. After each conversion the hold node is reset differentially using a core NFET driven by a 1.1V buffer. The 10b DAC consists of two identical 5b halves separated by a bridging capacitor, Cbridge. Cbridge is sized to provide approximately 0.8b of redundancy between the MSB and LSB halves, enabling capacitor mismatch in the MSB half to be corrected digitally. The DAC is controlled by decision latches and uses the split-capacitor switching scheme [1] to provide a constant common mode to the comparator during conversion. The DAC comprises approximately 60% of the 250fF/side hold capacitance, resulting in a 1.2Vppd full-scale range when a 1V reference is used.
Archive | 2005
Andrew Fernandez; Vamsi K. Srikantam; Robert M. R. Neff; Kenneth D. Poulton
Archive | 2005
Robert M. R. Neff
Archive | 2002
Kenneth D. Poulton; Robert M. R. Neff; Matthew S. Holcomb; James Kang
Archive | 2003
Ken Poulton; Robert M. R. Neff; Brian D. Setterberg; Bernd Wuppermann; Tom Kopley; Robert Jewett; Jorge Pernillo; Charlie Irawan Tan; Allen Montijo
Archive | 2002
Kenneth D. Poulton; Thomas Edward Kopley; Robert M. R. Neff
Archive | 2001
Robert M. R. Neff
Archive | 2003
Robert M. R. Neff