Bernhard Liegl

Optimization of segmented alignment marks for advanced semiconductor fabrication processes

The continued downscaling of semiconductor fabrication ground rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment. Past experiences indicate that good alignment depends largely on alignment signal quality, which, however, can be strongly affected by chip design and various fabrication processes. Under some extreme circumstances, they can even be reduced to the non- usable limit. Therefore, a systematic understanding of alignment marks and a method to predict alignment performance based on mark design are necessary. Motivated by this, we have performed a detailed study of bright field segmented alignment marks that are used in current state-of- the-art fabrication processes. We find that alignment marks at different lithographic levels can be organized into four basic categories: trench mark, metal mark, damascene mark, and combo mark. The basic principles of these four types of marks turn out to be so similar that they can be characterized within the theoretical framework of a simple model based on optical gratings. An analytic expression has been developed for such model and it has been tested using computer simulation with the rigorous time-domain finite- difference (TD-FD) algorithm TEMPEST. Consistent results have been obtained; indicating that mark signal can be significantly improved through the optimization of mark lateral dimensions, such as segment pitch and segment width. We have also compared simulation studies against experimental data for alignment marks at one typical lithographic level and a good agreement is found.

Is model-based optical proximity correction ready for manufacturing? Study on 0.12- and 0.175-μm DRAM technology

Two full-chip OPC approaches, a traditional rule-based approach and a more recent model-based approach are compared on DRAM applications using both ArF and KrF lithography, with off-axis illumination and phase shift masks. The similarities and differences between these two OPC approaches are compared in detail with selected one- and two-dimensional layout situations. Our results from the model-based approach show good line width control for one- dimensional structures and improved line-end printing for two-dimensional structures; however, results also show severe process window limitations for some layouts. The cause of the process window limitations with the model-based approach are discussed. To address the process window limitations in the model-based approach, a rule-based pre- correction was used to ensure adequate process window at deviated dose and focus conditions. With pre-correction combined with the model-based approach, our wafer data shows good correction quality and process window.

Lithography process cost considerations for 120-nm groundrules

In the near future semiconductor manufacturing will continue to push minimum feature sizes towards and below dimensions of a tenth of a micron. The lithographic patterning process is particularly challenged to support this trend with an every-higher optical resolution. A variety of resolution enhancing technologies are currently developed to encounter this challenge. Processes with decreased wavelength, techniques using strong phase shifting and thin film imaging will compete in terms of optical performance and process cost-of-ownership over the next few years. This paper compares cost-of-ownership of major lithography options for memory wafer structuring at 120nm ground rules or below. ArF lithography, alternating phase shift masks and multi-layer resist techniques are the selected candidates for a process cost analysis. Their cost-of-ownership relevant characteristics are identified and quantified with focus on consistency. This is the basis for a cost analysis and will support a constructive discussion about process feasibility.