Gary Williams

Ultrafast wafer alignment simulation based on thin film theory

The shrink of semiconductor fabrication ground rule continues to follow Moores law over the past years. However, at the 100 nm node, the fabrication cost starts to rise rapidly. This is mainly due tot he increase of complexity in the fabrication process, including the use of hard masks, planarization, resolution enhancement techniques, etc. Smaller device sizes require higher alignment tolerances. Also, higher degree of complexity makes alignment detection more difficult. For example, planarization techniques may destroy mark topography; hard masks may optically bury alignment marks, and more film layers makes the alignment signal more susceptible to process variations. Therefore in order to achieve reliable alignment, it is absolutely critical to develop an accurate and fast simulation software that can characterize alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment performance based on the film stack structure. In this paper, we will demonstrate that we have built an extremely fast alignment signal simulator for both direct imaging and diffractive detection system based on simple optical theory. We will demonstrate through examples using our advanced DRAM products that it is capable of accurately mapping the multi-dimensional parameter space spanned by various film thickness parameters within a short period of time, which allows both on-the-fly feedback in alignment performance and alignment optimization.

Optimization of segmented alignment marks for advanced semiconductor fabrication processes

The continued downscaling of semiconductor fabrication ground rule has imposed increasingly tighter overlay tolerances, which becomes very challenging at the 100 nm lithographic node. Such tight tolerances will require very high performance in alignment. Past experiences indicate that good alignment depends largely on alignment signal quality, which, however, can be strongly affected by chip design and various fabrication processes. Under some extreme circumstances, they can even be reduced to the non- usable limit. Therefore, a systematic understanding of alignment marks and a method to predict alignment performance based on mark design are necessary. Motivated by this, we have performed a detailed study of bright field segmented alignment marks that are used in current state-of- the-art fabrication processes. We find that alignment marks at different lithographic levels can be organized into four basic categories: trench mark, metal mark, damascene mark, and combo mark. The basic principles of these four types of marks turn out to be so similar that they can be characterized within the theoretical framework of a simple model based on optical gratings. An analytic expression has been developed for such model and it has been tested using computer simulation with the rigorous time-domain finite- difference (TD-FD) algorithm TEMPEST. Consistent results have been obtained; indicating that mark signal can be significantly improved through the optimization of mark lateral dimensions, such as segment pitch and segment width. We have also compared simulation studies against experimental data for alignment marks at one typical lithographic level and a good agreement is found.