Bernhard Lustig

Integrated CMOS circuit arrangement and method for the manufacture thereof

Method for producing a gate electrode for an MOS structure

Testable redundancy decoder of an integrated semiconductor memory

Circuit arrangement for testing a semiconductor memory by means of parallel tests using various test bit patterns

MOS-Transistor und Verfahren zu dessen Herstellung

Redundancy decoder for an integrated semiconductor memory

CMOS IC, e.g. an SRAM or DRAM cell array, has paired NMOS transistors and PMOS transistors with different operating voltages provided by different gate electrode compositions

Gate electrode mfg. method for MOS structure

An integrated circuit device and process for their preparation

Integrierte Schaltungsanordnung und Verfahren zu deren Herstellung An integrated circuit assembly and method for their preparation