Bertrand Pelloux-Prayer

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1].

6T SRAM design for wide voltage range in 28nm FDSOI

Unique features of the 28nm ultra-thin body and buried oxide (UTBB) FDSOI technology enable the operation of SRAM in a wide voltage range. Minimum operating voltage limitations of a high-density (HD) 6-transistor (6T) SRAM can be overcome by using a single p-well (SPW) bitcell design in FDSOI. Transient simulations of dynamic failure metrics suggest that a HD 6T SPW array with 128 cells per bitline operates down to 0.65V in typical conditions with no assist techniques. In addition, a wide back-bias voltage range enables run-time tradeoffs between the low leakage current in the sleep mode and the short access time in the active mode, making it attractive for high-performance portable applications.

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

Planar fully-depleted SOI technology is becoming mainstream within STMicroelectronics, targeting modern mobile and consumer multimedia markets. This technology combines high performance and low power consumption, complemented by an excellent responsiveness to power management design techniques. The fabrication process is comparatively simple and is a low-risk evolutionary step from conventional planar bulk CMOS. At 28nm, we find that planar FD more than matches the peak performance of “G”-type bulk technology, at the cost and complexity of a low-power type technology, with better power efficiency across use cases than any of the conventional bulk CMOS flavors. FD implementation of a representative design offers 1.6×-7× speedup compared to bulk across a range of supply voltages.

A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking

Wide-voltage-range-operation DSPs bring more versatility to achieve high energy efficiency in mobile applications to increase signal processing complexity and handle a large range of performance specifications. This paper describes a 32b DSP fabricated in 28nm UTBB FDSOI technology [1]. Body-bias-voltage (VBB) scaling from 0V up to ±2V (Pwell/Nwell) decreases the DSP core VDDMIN to 397mV and increases clock frequency by +400% at 500mV and +114% at 1.3V. In addition to technology gains, dedicated design features are included to increase frequency over the full VDD range, considering parameter variations. As depicted in Fig. 27.1.1, the 32b datapath VLIW DSP is organized around a MAC dedicated to complex arithmetic and two dedicated operators: a cordic/divider and a compare/select. Data enters the circuit through a serial interface and code is run from a 64×32b register file. It has been shown in [1] that a given operating frequency can be achieved at a lower VDD in UTBB FDSOI compared to bulk by applying a forward-body bias. An additional design step is achieved in this work by (1) increasing the frequency at low VDD thanks to a specific selection and design of standard cells with respect to power vs. performance and (2) dynamically tracking the maximum frequency to cope with variations.

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder

A minimum design effort methodology to enable energy efficient and variability tolerant ultra-wide voltage-range frame error-decoder design in 28nm CMOS technology is presented. Critical aspects of a digital design development - standard cells, interface, clock tree and implementation - were optimized enabling 1.0V to 350mV functionality, 10x energy reduction, 10MHz to 700MHz frequency, and a reduction of the variability enabling industrial yield at ultra-low voltage. The same design was then ported to 28nm Fully-Depleted SOI (FDSOI), offering up-to 2x higher energy efficiency while validating the design methodology robustness.

DTMOS power switch in 28 nm UTBB FD-SOI technology

Ultra-Thin Body and Box (UTBB) Fully Depleted Silicon-On-Insulator (FD-SOI) Technology has become mainstream in the industry with the objective to serve a wide spectrum of mobile multimedia products [1]. Transistors (fig 1) are fabricated in a 7nm thin layer of silicon sitting (Tsi) over a 25nm buried oxide (Tbox). Thanks to its better electrostatic control [2]; UTBB FD-SOI technology brings a significant improvement in terms of performance and power saving, complemented by an excellent responsiveness to power management design techniques for energy efficiency optimization. However, looking for a steady increase in performance for a voltage supply value constantly lowered with the evolution of technologies, BULK or FD-SOI, involves a decrease in the threshold voltage (Vt) and leads to an increase of the stand-by leakage current, requiring the implementation of a leakage current reduction technique.

Experimental model of adaptive body biasing for energy efficiency in 28nm UTBB FD-SOI

In Ultra-Thin Body and BOX Fully Depleted Silicon-On-Insulator (UTBB FD-SOI) technology, body biasing can be used to achieve better energy efficiency. We propose a simple Time, Energy, Power (TEP) model based on Ring Oscillators (RO) measurements to predict optimal (Vdd;Vbb) point for complex circuits and validate it against direct experimental measurements. The model predicted Adaptive Forward Body Biasing (A-FBB) energy gain is compared to Vdd only methods: supply scaling, Vdd hopping and power gating.

Multiple-pulse dynamic stability and failure analysis of low-voltage 6T-SRAM bitcells in 28nm UTBB-FDSOI

This work investigates the effects of process variability on the dynamic stability of a 6-Transistor Static Random Access Memory bitcell manufactured in 28nm Ultra-Thin Body and Buried Oxide Fully-Depleted Silicon-On-Insulator (UTBB-FDSOI) technology node. The study is carried out for two different well architectures: single-well (peculiar to UTBB-FDSOI) and dual-well (like in standard CMOS), through Most-Probable Failure Point tracking methodology coupled with Importance Sampling. Different failure mechanisms appearing under different operating conditions are discussed. We show that the Read-After-Write failure criterion based on multiple Word-Line pulses is the most accurate way to evaluate bitcell failure rate and thus its yield under realistic dynamic conditions. The methodology exposed in this work is applied to demonstrate the superior properties of the single-well architecture.

Performance analysis of multi-V T design solutions in 28nm UTBB FD-SOI technology

UTBB FD-SOI technology is able to reach very high speeds thanks to flip-Wells variant which enables low-VT (LVT) tuning. This approach appears to be the best design option to catch high CPU frequencies or/and optimal energy consumption. To save power when logical paths are not critical, regular-VT (RVT) transistors, which seat on classical-Wells, cannot be abutted to LVT transistors because of the Well bias conflicts. To overcome these multi-VT constraints, several innovative cointegration schemes based on single-Well (SW) approaches have been designed in 28nm UTBB FD-SOI technology and validated by silicon results.

0.42-to-1.20V read assist circuit for SRAMs in CMOS 65nm

This work presents an ultra-low voltage SRAM read frequency boost circuit developed in 65nm to cover the lack of reliable sense amplifiers. This circuit enables full swing read speed-up and bitline leakage compensation from 1.2V to 0.42V. Embedded in a 65nm 32kb 10T SRAM, it offers 10% frequency gain and 10-to-90% leakage energy reduction from nominal to ultra-low voltage supply.