Sylvain Clerc

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.

8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing

A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current at negative temperatures, the need for an extra digital supply IO, and the clocking power costs faced by the internet-of-things (IoT) and wearable systems. The system includes: 1) an all-digital single-supply open-loop clock multiplier achieving 1.51 pJ/cycle; 2) a 0.33V/0.45V dual-mode switched-network-capacitor DC-DC down converter from a 1.1V logic supply, reaching 75% conversion efficiency in both modes; 3) a closed-loop low-invasiveness timing monitoring system dynamically compensating device centering and temperature changes, enabling constant frequency operation down to -40°C at 20MHz (1MHz) in EE (LL) mode. The system fully exploits forward body bias (FBB) available in 28nm UTBB FDSOI with LVT transistors.

A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications

Ultra-low voltage is now a well known solution for energy constrained applications designed using nanometric process technologies. This work is focused on setting-up an automated methodology to enable the design of ultra-low voltage digital circuits exclusively using standard EDA tools. To achieve this goal, a 0.35V energy-delay optimized library was developed. This library, fully compliant with standard library design flow and characterization, was verified through the design and fabrication of a BCH decoder circuit, following a standard front-end to back-end flow. It performs at 457 kHz, with a total energy consumption of 2.9fJ per cycle.

A 460MHz at 397mV, 2.6GHz at 1.3V, 32b VLIW DSP, embedding F MAX tracking

Wide-voltage-range-operation DSPs bring more versatility to achieve high energy efficiency in mobile applications to increase signal processing complexity and handle a large range of performance specifications. This paper describes a 32b DSP fabricated in 28nm UTBB FDSOI technology [1]. Body-bias-voltage (VBB) scaling from 0V up to ±2V (Pwell/Nwell) decreases the DSP core VDDMIN to 397mV and increases clock frequency by +400% at 500mV and +114% at 1.3V. In addition to technology gains, dedicated design features are included to increase frequency over the full VDD range, considering parameter variations. As depicted in Fig. 27.1.1, the 32b datapath VLIW DSP is organized around a MAC dedicated to complex arithmetic and two dedicated operators: a cordic/divider and a compare/select. Data enters the circuit through a serial interface and code is run from a 64×32b register file. It has been shown in [1] that a given operating frequency can be achieved at a lower VDD in UTBB FDSOI compared to bulk by applying a forward-body bias. An additional design step is achieved in this work by (1) increasing the frequency at low VDD thanks to a specific selection and design of standard cells with respect to power vs. performance and (2) dynamically tracking the maximum frequency to cope with variations.

Scalable 0.35 V to 1.2 V SRAM Bitcell Design From 65 nm CMOS to 28 nm FDSOI

This work presents a method for the design and characterization of a scalable ultra-wide voltage range static random access memory using an optimized 10 transistor bitcell, targeting minimum operating voltage, high yield and a Silicon-CAD correlation within 5%. The method is based on both static and dynamic metrics. The experimental validation was first performed in BULK CMOS 65 nm on a 32 kb memory array, then applied in 28 nm FDSOI on a 64 kb memory array. Over 10× energy reduction is achieved across a wide voltage range, i.e., from 1.2 V to 0.35 V while achieving high speed at the nominal voltage, i.e., 485 MHz in 65 nm BULK and 1 GHz in 28 nm FDSOI.

New D-Flip-Flop Design in 65 nm CMOS for Improved SEU and Low Power Overhead at System Level

A new latch architecture based on a switchable hysteresis mechanism to improve the SEU hardness in hold mode and limit the delay penalty during write operation is proposed. This latch relies on the Schmitt trigger inverter schematic and has been named the Robust Schmitt Trigger (RST) latch. RST latch has been implemented in a 65 nm radiation test vehicle and upset rates have been measured during proton irradiations. Our design solution enhanced the SEU cross-section and divides by 2 the system level power consumption penalty compared to a DICE based design. The RST latch is an alternative between the DICE latch and the reference latch for soft radiative environments.

Experimental characterization of process corners effect on SRAM alpha and neutron Soft Error Rates

This paper shows alpha and neutron experimental Soft Error Rate characterization of a SRAM test vehicle processed with different process corners in order to emulate the variability encountered in volume production. It allows assessing large variability effects with few samples that are compatible with accelerated SER testing. This allows investigating the effect of variability in mass-production on soft error rate of deca-nanometric technologies.

28nm CMOS, energy efficient and variability tolerant, 350mV-to-1.0V, 10MHz/700MHz, 252bits frame error-decoder

A minimum design effort methodology to enable energy efficient and variability tolerant ultra-wide voltage-range frame error-decoder design in 28nm CMOS technology is presented. Critical aspects of a digital design development - standard cells, interface, clock tree and implementation - were optimized enabling 1.0V to 350mV functionality, 10x energy reduction, 10MHz to 700MHz frequency, and a reduction of the variability enabling industrial yield at ultra-low voltage. The same design was then ported to 28nm Fully-Depleted SOI (FDSOI), offering up-to 2x higher energy efficiency while validating the design methodology robustness.

Heavy ions test result on a 65nm Sparc-V8 radiation-hard microprocessor

In this paper, we present the heavy-ion radiation test results for a 7-stage SPARC micro-processor. Special software handlers enabled fine grained classification of the types of crashes. The measured crash cross sections are compared with those predicted by fault injection simulation.

A 65nm SRAM achieving 250mV retention and 350mV, 1MHz, 55fJ/bit access energy, with bit-interleaved radiation Soft Error tolerance

An Ultra Low Voltage memory was fabricated in 65nm CMOS with an optimized 10 transistors bitcell. It withstands 1.2V down to 0.35V voltage range, achieves 55fJ/bit energy access at 0.35V and exhibits wafer level yield above 95% at 0.4V, 1MHz. Packaged parts test show 0.32V minimum operating voltage at 500kHz, up to 17X energy gain per operation and 250mV retention voltage at 125°C. The memory terrestrial radiation Soft Error Rate was characterized with no multibit errors reported, enabling radiation reliability through bit-interleaving combined with error correcting code.