Jean-Philippe Noel

Can we go towards true 3-D architectures?

Thanks to recent technology advances, the exploration of the vertical dimension has been shown to be more than a dream for designers. Among those technologies, the vertical transistor has not been exploited yet. This paper describes a novel implementation of logic gates fully benefiting of nanowire-based vertical transistors embedded within the metal lines. The logic design in this technology is explored and its performance is evaluated. A comparison made on an equivalent technology node shows that our cells reduce area and delay by a factor of 31x and 2x respectively. Large reconfigurable logic circuits have been benchmarked showing an improvement of area and delay by 46% and 48% on average.

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology

This paper presents an IEEE 802.11n Low-Density Parity-Check (LDPC) decoder implemented in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FDSOI), and demonstrates the performance gains of this circuit vs. 28nm LP high-κ metal-gate CMOS bulk technology. It also introduces extended body bias (BB) design techniques to take advantage of specific features of the UTBB technology to overcome the +/-300mV BB range limitation of conventional bulk technologies [1].

A 460 MHz at 397 mV, 2.6 GHz at 1.3 V, 32 bits VLIW DSP Embedding F MAX Tracking

Wide voltage range operation for DSPs brings more versatility to achieve high energy efficiency in mobile applications. This paper describes a 32 bits DSP fabricated in 28 nm Ultra Thin Body and Box FDSOI technology. Body Biasing Voltage (VBB) scaling from 0 V up to ±2 V decreases the core VDDMIN to 397 mV and increases clock frequency by +400%@500 mV and +114%@1.3 V. The DSP frequency measurements show 2.6 GHz@1.3 V(VDD)@2 V(VBB) and 460 MHz@397 mV(VDD)@2 V(VBB). The lowest peak energy efficiency is measured at 62 pJ/op at 0.53 V. In addition to technological gains, maximum frequency tracking design techniques are proposed for wide voltage range operation. On silicon, at 0.6 V, those techniques allow high energy gain of 40.6% w.r.t. a worst case corner approach.

Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs

Todays MPSoC applications are requiring a convergence between very high speed and ultra low power. Ultra Wide Voltage Range (UWVR) capability appears as a solution for high energy efficiency with the objective to improve the speed at very low voltage and decrease the power at high speed. Using Fully Depleted Silicon-On-Insulator (FDSOI) devices significantly improves the trade-off between leakage, variability and speed even at low-voltage. A full design framework is presented for UWVR operation using FDSOI Ultra Thin Body and Box technology considering power management, multi-VT enablement, standard cells design and SRAM bitcells. Technology performances are demonstrated on a ARM A9 critical path showing a speed increase from 40% to 200% without added energy cost. In opposite, when performance is not required, FDSOI enables to reduce leakage power up to 10X using Reverse Body Biasing.

Fine grain multi-V T co-integration methodology in UTBB FD-SOI technology

Ultra-Thin Body and BOX Fully-Depleted SOI (UTBB FD-SOI) technology is one of two candidate technologies for replacing Bulk technology at sub-20 nm nodes. Although it represents a smooth transition from Bulk, i.e. being a planar technology with a similar gate stack and a simpler front-end-of-line process, it enables a reinforced process-design co-optimization thanks to Well engineering capability. This added degree of freedom has unleashed the creativity of designers and technologists, creating objects like `flip-Well and `single-Well logic gates. This paper presents the state-of-the-art of UTBB FD-SOI implementation strategies and solves the multi-VT constrains thanks to innovative fine grain co-integration approaches.

Optimization of a voltage sense amplifier operating in ultra wide voltage range with back bias design techniques in 28nm UTBB FD-SOI technology

Advanced SoC designs regularly use Dynamic Voltage and Frequency Scaling (DVFS) to achieve high performance and low power targets of portable systems. In this paper, we focus on optimization of a Voltage Sense Amplifier (VSA) in 28nm Ultra-Thin Body and BOX Fully Depleted SOI (UTBB FD-SOI) technology to achieve high performance operations over the Ultra Wide Voltage Range (UWVR) from 1.3V to 0.4V. We use Flip-Well design methodology along with forward body bias modulation to extend operation range of the VSA and also reduce sense amplifier read time by 28%, while saving power consumption by up to 59% compared to Bulk technology.

Low Standby Power Capacitively Coupled Sense Amplifier for wide voltage range operation of dual rail SRAMs

Dual Rail SRAMs are widely used to enable Dynamic Voltage and Frequency Scaling (DVFS) in SRAMs where array voltage cannot be scaled down. DVFS operating points are limited by maximum differential supported between two supplies of the SRAM. To extend gains of DVFS, we propose a Low Standby Power - Capacitively Coupled Sense Amplifier (LSTP-C2SA) that enables further lowering of periphery supply in Dual Rail SRAMs without leading to SRAM cell instability. We present a design method to optimally size the coupling capacitance in LSTP-C2SAs. Designs with LSTP-C2SA are shown to consume 43% lesser read power in DVFS operation at 0.4V in 28nm UTBB FD-SOI when compared to an implementation with standard latch sense amplifier. Silicon measurements confirm LSTP-C2SA functionality at 0.35V.

Design methodology for area and energy efficient OxRAM-based non-volatile flip-flop

With the introduction of the Internet of Things (IoT), power consumption became a major design issue in modern system-on-chips. In advanced technologies, leakage power has become a dominant component, especially during sleep periods. Leakage mainly comes from volatile memory elements, e.g., flip-flops that cannot be power-gated in order to retain their states. Non-Volatile Flip-Flop (NVFF) using emerging memory technologies, such as Resistive Random Access Memories (RRAM), are popular solutions to address this issue. In NVFF design, the resistance values of the memory element have a direct impact on the area and energy overhead of the structure. In this paper, we present a design methodology for area and energy efficient RRAM-based NVFF. By characterizing the optimal lower bound of the RRAM resistance ratio required for properly restoring the FF, the store and restore operations can be performed using optimal programming circuit area and energy. Four Transmission-Gate (TG) NVFF topologies implemented in 180nm CMOS technology were analyzed using the proposed methodology. The presented methodology shows that differential NVFF provides minimum restore resistance ratio down to 1.02 considering CMOS and RRAM variability. This enables improvements in terms of store energy (34%) and area overhead (40%) compared to reported state-of-the-art NV-TGFFs design approaches.