Bertrand Zavidovique

Content based image retrieval using motif cooccurrence matrix

We present a new technique for content based image retrieval using motif cooccurrence matrix (MCM). The MCM is derived from the motif transformed image. The whole image is divided into 2×2 pixel grids. Each grid is replaced by a scan motif that minimizes the local gradient while traversing the 2×2 grid forming a motif transformed image. The MCM is then defined as a 3D matrix whose (i,j,k) entry denotes the probability of finding a motif i at a distance k from the motif j in the transformed image. Conceptually, the MCM is quite similar to the color cooccurrence matrix (CCM), however, the retrieval using the MCM is better than the CCM since it captures the third order image statistics in the local neighborhood. Experiments confirm that the use of MCM considerably improves the retrieval performance.

Median binary pattern for textures classification

A texture classification method using a binary texture metric is presented. The method consists of extracting local structures and describing their distribution by a global approach. Texture primitives are determined by a localized thresholding against the local median. The local spatial signature of the thresholded image is uniquely encoded as a scalar value, whose histogram helps characterize the overall texture. A multi resolution approach has been tried to handle variations in scale. Also, the encoding scheme facilitates a rich class of equivalent structures related by image rotation. Then, we demonstrate - using a set of classifications, that the proposed method significantly improves the capability of texture recognition and outperforms classical algorithms.

Rotationally Invariant Hashing of Median Binary Patterns for Texture Classification

We present a novel image feature descriptor for rotationally invariant 2D texture classification. This extends our previous work on noise-resistant and intensity-shift invariant median binary patterns (MBPs), which use binary pattern vectors based on adaptive median thresholding. In this paper the MBPs are hashed to a binary chain or equivalence class using a circular bit-shift operator. One binary pattern vector (ie.smallest in value) from the group is selected to represent the equivalence class. The resolution and rotation invariant MBP (MBP ROT) texture descriptor is the distribution of these representative binary patterns in the image at one or more scales. A special subset of these rotation and scale invariant representative binary patterns termed uniformpatterns leads to a more compact and robust MBP descriptor (MBP UNIF) that outperforms the rotation invariant uniform local binary patterns (LBP UNIF). We quantitatively compare and demonstrate the advantage of the new MBP texture descriptors for classification using the Brodatz and Outex texture dictionaries.

Hardware Design of a Binary Integer Decimal-based IEEE P754 Rounding Unit

Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754). In this paper, we present a hardware design for a rounding unit for 64-bit DFP numbers (decimal 64) that use the IEEE P754 binary encoding of DFP numbers, which is widely known as the Binary Integer Decimal (BID) encoding. We summarize the technique used for rounding, present the theory and design of the BID rounding unit, and evaluate its critical path delay, latency, and area for combinational and pipelined designs. Over 86% of the rounding units area is due to a 55-bit by 54-bit binary multiplier, which can be shared with a double-precision binary floating-point multiplier. To our knowledge, this is the first hardware design for rounding IEEE P754 BID-encoded DFP numbers.Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it were recently added to the draft revision of the IEEE 754 Standard (IEEE P754). In this paper, we present a hardware design for a rounding unit for 64-bit DFP numbers (decimal 64) that use the IEEE P754 binary encoding of DFP numbers, which is widely known as the Binary Integer Decimal (BID) encoding. We summarize the technique used for rounding, present the theory and design of the BID rounding unit, and evaluate its critical path delay, latency, and area for combinational and pipelined designs. Over 86% of the rounding units area is due to a 55-bit by 54-bit binary multiplier, which can be shared with a double-precision binary floating-point multiplier. To our knowledge, this is the first hardware design for rounding IEEE P754 BID-encoded DFP numbers.

Efficient cumulative matching for image registration

A new level-line registration technique is proposed for image transform estimation. This approach is robust towards contrast changes, does not require any estimate of the unknown transformation between images and tackles very challenging situations that usually lead to pairing ambiguities, like repetitive patterns in the images. The registration by itself is performed through efficient level-line cumulative matching based on a multi-stage primitive election procedure. Each stage provides a coarse estimate of the transformation that the next stage gets to refine. Even if we deal in this paper with similarity transform (rotation, scale and translation), our approach can be adapted to more general transformations.

Light speed labeling: efficient connected component labeling on RISC architectures

This article introduces two fast algorithms for connected component Labeling of binary images, a peculiar case of coloring. The first one, SelkowDT is pixel-based and a Selkow’s algorithm combined with the decision tree optimization technique. The second one called light speed labeling is segment-based line-relative labeling and was especially thought for commodity RISC architectures. An extensive benchmark on both structured and unstructured images substantiates that these two algorithms, the way they were designed, run faster than Wu’s algorithm claimed to be the world fastest in 2007. Also they both show greater data independency hence runtime predictability.

Design of a half-toning integrated circuit based on analog quadratic minimization by non linear multistage switched capacitor network

As part of an effort to build a smart sensor, the authors present the design of a neural network performing the minimization of a quadratic distance between the analog acquired picture and a convolution of the resulting halftoned binary picture. It is shown that using a diffusion kernel and switched-capacitor networks results in an effective halftoning circuit, well-suited to a very compact CMOS implementation. It is concluded that this design methodology can be utilized for the implementation of a large class of early or low-level vision problems, expressed as quadratic cost function minimization.<<ETX>>

A data-flow processor for real-time low-level image processing

A chip featuring two coupled data-flow processors (DFPs) has been designed. It is to be mesh-connected into large processor arrays dedicated primarily to image processing. Each processor operates on 25 Mbyte/s data flows and performs up to 50 million 8- or 16-b arithmetic operations per second. The chip has been processed in a 1- mu m CMOS technology. It includes 160000 transistors in a 84 mm/sup 2/ die size area; its clock is at 25 MHz; and it is packaged in a 144-pin PGA package. The approach is to perform computations on the fly on a data flow that comes from a digital video camera. The set of available operators on the DFP has been defined to cover as widely as possible the range of low-level image processing functions.<<ETX>>

Region-based CBIR in GIS with local space filling curves to spatial representation

In this paper we present a region-based retrieval method for satellite images using motif co-occurrence matrix (MCM) in conjunction with spatial relationships. Each image is decomposed into coherent segments, MCM is computed for each region and the spatial relationship among them are evaluated by using a *-tree representation. The image is represented by an attributed relational graph (ARG) where nodes contain the visual feature (MCM) and edges represent spatial relationship. Principal component analysis show the usefulness of MCM as a feature.

Image processing in a tree of peano coded images

The authors investigate some attractive features of the 1-D sequence of pixels produced by the peano traversal of an image. They introduce two new hardware operations called bit-spreaded-meshing and its inverse brit-collation to produce and invert the sequence in real-time. A compact binary tree built using this sequence at its base implicitly contains the well known quadtree of the image also. The binary tree representation supports efficient design and implementation of divide and conquer algorithms. Its construction is readily extendable to higher dimensional images. They present a global optimization algorithm for image segmentation whose design is based on the binary tree. It produces a minimal cutset of homogeneous nodes in the tree using a dynamic programming technique. The experimental results assert the merit of the binary tree based implementation compared to its counterpart the quadtree.