Patrick Garda

Optical cellular processor architecture. 1 : Principles

General characteristics and advantages of 2-D optical cellular processors are listed and discussed, with reference to the concepts of cellular automata, symbolic substitution, and neural nets. The role of optical interconnections and of quasilinear processing combining linear array operations and pointwise nonlinearities is highlighted. An architecture for optical implementation of cellular automata is introduced; it features high density 3-D optical shift-invariant interconnections and programmability of the interconnection pattern through adequate use of holographic connectors.

A Review of the CMOS Buried Double Junction (BDJ) Photodetector and its Applications

A CMOS Buried Double Junction PN (BDJ) photodetector consists of two vertically-stacked photodiodes. It can be operated as a photodiode with improved performance and wavelength-sensitive response. This paper presents a review of this device and its applications. The CMOS implementation and operating principle are firstly described. This includes the description of several key aspects directly related to the device performances, such as surface reflection, photon absorption and electron-hole pair generation, photocurrent and dark current generation, etc. SPICE modelling of the detector is then presented. Next, design and process considerations are proposed in order to improve the BDJ performance. Finally, several BDJ-detector-based image sensors provide a survey of their applications.

Motion detection, labeling, data association and tracking, in real-time on RISC computer

This article introduces some algorithms for motion detection and tracking. To be able to track moving objects, the analysis rate must be fast enough in order to keep the considered movements slow (and the features of the objects not changing too fast). We present a Markov random field-based motion detection algorithm running in real time on a Pentium II and DSP C6x. For the medium level, we have developed a fast labelling algorithm; a benchmark is provided. The high level is fast because the previous processing steps are running at a faster rate than the video rate.

Empirical Method Based on Neural Networks for Analog Power Modeling

We introduce an empirical method for power consumption modeling of analog components at system level. The principal step of this method uses neural networks to approximate the mathematical curve of the power consumption as a function of the inputs and parameters of the analog component. For a node of a wireless sensors network, we found an average error of 1.53% with a maximum error of 3.06% between our estimation and the measured power consumption. This novel method is suitable for Platform-Based Design and has three key features for architecture exploration purposes. Firstly, the method is generic as it can be applied to any analog component in any modeling and simulation environment. Secondly, the method is suitable for the total (analog and digital) power consumption estimation of a heterogeneous system. Thirdly, the method provides an online estimation of the instantaneous power consumption of analog blocks.

A neural halftoning algorithm suiting VLSI implementation

Halftoning is presented as an application where the use of simple neural networks proves to be of immediate interest. Halftoning is a nonstandard A/D conversion that is treated as an optimization problem, subject to a frequency-weighted mean-square-error (MSE) criterion. The frequency weight is implemented by means of a specific neural interconnection network based on current diffusion in resistive grids. This physical choice not only leads to a dramatically compact VLSI switch capacitor implementation, but also turns the whole process into a clean 2-D isotropic generalization of Sigma - Delta modulation. Isotropy and shift-invariance cooperate within the same halftoning process for the sake of image rendition. The performances prove equal to the deep underlying harmony between the theoretical, algorithmic, and material aspects of the procedure.<<ETX>>

Optical generation of random-number arrays for on-chip massively parallel Monte Carlo cellular processors

Stochastic optical phenomena can be used for generation of random-bit arrays with a prescribed probability law that may vary in space and in time. This is useful for implementation of Monte Carlo algorithms, including simulated annealing, with a high recursion rate by monolithic massively parallel arrays of processing elements. Each processing element includes a photosensor. The use and advantages of speckle and of microchannel-plate image intensifiers amplifying single-photon events are considered.

An Emulation-Based Method for Lifetime Estimation of Wireless Sensor Networks

Lifetime estimation in Wireless Sensor Networks (WSN) is crucial to ensure that the network will last long enough (low maintenance cost) while not being over-dimensioned (low initial cost). Existing solutions have at least one of the two following limitations: (1) they are based on theoretical models or high-level protocol implementations, overlooking low-level (e.g., hardware, driver, etc.) constraints which we find have a significant impact on lifetime, and (2) they use an ideal battery model which over-estimates lifetime due to its constant voltage and its inability to model the non-linear properties of real batteries. We introduce a method for WSN lifetime estimation that operates on compiled firmware images and models the complex behavior of batteries. We use the MSPSim/Cooja node emulator and network simulator to run the application in a cycle-accurate manner and log all component states. We then feed the log into our lifetime estimation framework, which models the nodes and their batteries based on both technical and experimental specifications. In a case study of a Contiki RPL/6LoWPAN application, we identify and resolve several low-level implementation issues, thereby increasing the predicted network lifetime from 134 to 484 days. We compare our battery model to the ideal battery model and to the lifetime estimation based on the radio duty cycle, and find that there is an average over-estimation of 36% and 76% respectively.

Modelling field bus communications in mixed-signal embedded systems

We present a modelling platform using the SystemC-AMS language to simulate field bus communications for embedded systems. Our platform includes the model of an I/O controller IP (in this specific case an C controller) that interfaces a master microprocessor with its peripherals on the field bus. Our platform shows the execution of the embedded software and its analog response on the lines of the bus. Moreover, it also takes into account the influence of the circuitss I/O by including their IBIS models in the SystemC-AMS description, as well as the bus lines imperfections. Finally, we present simulation results to validate our platform and measure the overhead introduced by SystemC-AMS over a pure digital SystemC simulation.

Wireless communicative stent for follow-up of abdominal aortic aneurysm

An abdominal aortic aneurysm (AAA) is a dilatation of the aorta at the abdominal level, which rupture is a life threatening complication. Recent treatment of AAA consists in endovascular treatment with covered stent grafts. Despite improving devices, this treatment is still associated with close to 25% of failure related to persisting pressure into the excluded aneurismal sac. The follow-up becomes thus crucial and demands frequent examinations (CT-scan, IRM) which are not so liable given the complications. In order to evaluate the post-operative period of an AAA treatment, we designed a communicative stent, comprising of an integrated pressure sensor. This paper presents the conception of a communicative sensor, the elaboration of a numerical model, and the development of an experimental testbench constituting the aortic flux across an AAA and allowing the optimization and validation of the measurement principle.

Fast triggering in high-energy physics experiments using hardware neural networks

High-energy physics experiments require high-speed triggering systems capable of performing complex pattern recognition at rates of Megahertz to Gigahertz. Neural networks implemented in hardware have been the solution of choice for certain experiments. The neural triggering problem is presented here via a detailed look at the H1 level 2 trigger at the HERA accelerator, Hamburg, Germany, followed by a section on the importance of hardware preprocessing for such systems, and finally some new architectural ideas for using field programmable gate arrays in very high-speed neural-network triggers at upcoming experiments.