Bibhu Datta Sahoo

A 12-Bit 200-MHz CMOS ADC

A pipelined ADC incorporates a blind LMS calibration algorithm to correct for capacitor mismatches, residue gain error, and op amp nonlinearity. The calibration applies 128 levels and their perturbed values, computing 128 local errors across the input range and driving the mean square of these errors to zero. Fabricated in 90-nm digital CMOS technology, the ADC achieves a DNL of 0.78 LSB, an INL of 1.7 LSB, and an SNDR of 62 dB at an analog input frequency of 91 MHz while consuming 348 mW from a 1.2 V supply.

A 10-b 1-GHz 33-mW CMOS ADC

This paper describes a pipelined analog-to-digital converter that resolves 4 b in its first stage and amplifies the residue by a factor of 2, thereby relaxing the opamp linearity, voltage swing, and gain requirements. Calibration in the digital domain removes the effect of capacitor mismatches and corrects for the gain error. Using a one-stage opamp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with a signal-to-(noise+distortion) ratio of 52.4 dB, achieving a figure of merit of 97 fJ/conversion-step.

An 8 Bit 4 GS/s 120 mW CMOS ADC

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

A 10-bit 1-GHz 33-mW CMOS ADC

A pipelined ADC digitally calibrates capacitor mismatches in its 4-bit first stage and the gain error in the first 5 stages. Using a one-stage op amp with a gain of 10 and realized in 65-nm CMOS technology, the ADC digitizes a 490-MHz input with an SNDR of 52.4 dB, achieving an FOM of 0.097pJ/conversion-step.

A fast simulator for pipelined A/D converters

A simulator for comprehensive analysis of pipelined A/D converters has been developed in MATLAB and compiled to an executable that can be run on various platforms. The simulator accepts user-specified parameters such as resolution per stage, number of stages, input and clock frequencies, input amplitude, op amp nonlinearity, capacitor mismatch, comparator offset, and clock jitter. The tool then provides the simulated performance in the form of residue plots, differential and integral nonlinearity profiles, output spectrum, and input-referred thermal noise. Compared with Cadences Spectre, the proposed simulator runs several orders of magnitude faster while incurring a small error.

An 8-Bit 4-GS/s 120-mW CMOS ADC

A time-interleaved ADC employs four pipelined time-interleaved channels along with a new timing mismatch detection algorithm and a high-resolution variable delay line. The digital background calibration technique suppresses the interchannel timing mismatches, achieving an SNDR of 44.4 dB and a figure of merit of 219 fJ/conversion-step in 65 nm CMOS technology.

U-PAS: A user-friendly ADC simulator for courses on analog design

A simulator with a graphical user interface has been developed for the analysis and design of pipelined analog-to-digital converters. The user can enter parameters such as resolution per stage, number of pipelined stages, input and clock frequencies, input amplitude, op amp nonlinearity, capacitor mismatch, and comparator offset. The simulator then computes various static and dynamic properties of the system such as residue plots, differential and integral nonlinearity profiles, output spectrum, and input-referred noise. Available as an executable code, the simulator can run on various platforms.

Thermal-Noise-Canceling Switched-Capacitor Circuit

Thermal noise has been a fundamental bottleneck in building high dynamic range switched capacitor (SC) circuits. This brief proposes an SC thermal-noise-canceling circuit. The technique, demonstrated using a unity-gain sample-and-hold amplifier (SHA) in IBM 32-nm silicon-on-insulator (SOI) process, gives 5.0-, 4.4-, and 3.7-dB improvements while operating at 100, 250, and 500 MHz, respectively, and consuming only 30% additional power as compared to 400% to get a similar improvement without noise cancelation.

Achieving Theoretical Limit of SFDR in Pipelined ADCs

In pipelined analog-to-digital converters (ADCs), the spurious free dynamic range (SFDR) and signal-to-noise ratio depend strongly on the precision with which the interstage gain and capacitor mismatch terms are estimated using digital calibration techniques. This paper introduces a dithering-based calibration technique, which facilitates accurate estimation of the interstage gain and capacitor mismatch term with minimal hardware overhead, thus realizing pipelined ADCs that achieve the theoretical maximum SFDR. The proposed technique is validated both at system level using MATLAB and then at circuit level. A prototype 12-bit pipelined ADC operating at 500 MHz was designed in 55-nm global foundry LP-CMOS process. The prototype 12-bit ADC realized with op amp that have open-loop gains as low as 54 dB, but linearity ≈100 dB achieves an SFDR of 100.13 dB when calibrated using the proposed technique.