Bidesh Chakraborty

Quick consensus through early disposal of faulty processes

This work reports an efficient solution for reaching agreement (consensus) among the processes of a distributed system. The better efficiency is achieved through early disposal of faulty processes while approaching for a consensus. The introduced network partitioning scheme further facilitates the progress by reducing the message exchange overhead. Simulation results establish that the proposed solution significantly reduces the message exchange complexity, in comparison to the schemes reported so far, simultaneously ensuring the fault-tolerance ability of a system as that of the known best results.

Design of coherence verification unit for CMPs realizing dragon protocol

The data coherence in Chip Multiprocessors (CMPs) cache system is to be more accurate and reliable. A system with single producer and multiple consumers uses update based coherence protocol (dragon). This work proposes an effective solution for coherence verification in dragon through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length cycle single attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of dragon. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.

Design of coherence verification unit for heterogeneous CMPs

In embedded SoC applications, the demand for integration of heterogeneous processors on a single chip is increasing. On-chip heterogeneity allows different processors to employ different cache coherence protocols which in turn add difficulties in the task of integrating different coherence protocols as well as realizing the task of coherence verification. This work first proposes an efficient mechanism for integrating update based as well as invalidation based coherence protocols in a heterogeneous Chip Multiprocessors (CMPs) cache system and then realizes a coherence verification logic to verify cache coherency in such a system. The verification logic design is based on the modular structure of Cellular Automata (CA). The special class of CA, referred to as SACA (single length cycle single attractor CA) has been employed to identify the inconsistencies in cache line states computed by cache coherence controller (CC). The simple hardware implementation of the CA based design realizes quick decision on the cache coherency with high accuracy.

A Segmented CA Based Approach to Test TSVs in 3D IC

A three-dimensional (3D) IC using through silicon via (TSV) has been found to be more effective to cope with the challenges faced by current 2D technologies. Post-bond testing of TSVs has been identified as a major challenge for yield assurance in 3D ICs. This work proposes a novel post-bond test scheme for TSVs in a 3D ICs. The solution/design is based on the modular structure of Cellular Automata (CA), a modeling tool invented by von Neumann and Stanislaw Ulam. A special class of CA referred to as SACA has been introduced to identify the defects in TSVs. The introduction of CA segmentation ensures better efficiency in the design, in terms of number of computations to detect the faulty TSVs.

Pre-bond Testing of TSVs in 3D IC Using Segmented Cellular Automata

Pre-bond testing of through silicon vias (TSVs) in 3D ICs is very challenging task. Reliability and correctness of 3D ICs consisting of numbers of TSVs have to be established. This paper presents an innovative pre-bond test method for TSVs in a 3D IC. The logic is devised around the cascadable arrangement of Cellular Automata (CA), discovered by von Neumann in the year of 1960. SACA, a designated class of CA, has been developed to diagnose conductor and insulator defects in TSVs. The segmentation of CA in the design assures more effectiveness, with respect to the number of computations to identify faulty TSVs. The implemented hardware realizes quick test of manufacturing TSV faults in the pre-bond phase.

A Cellular Automata Based BIST for Detecting NPSFs in High Speed Memories

Built-in-self-test (BIST) in memory is considered as most cost effective method for memory testing. In this work, we propose a cellular automata (CA) based BIST architecture to detect neighborhood pattern sensitive faults (NPSFs) in high speed memories. For implementation of the proposed CABIST, we employ 5-neighborhood periodic boundary CA (PBCA). Theory has been developed for two special classes of PBCA - single length cycle single attractor CA (SACA) and single length cycle two attractor CA (TACA) employed for the design. The proposed CABIST efficiently detects all NPSFs in memory devices at a lower cost compared to existing schemes.

Cellular Automata Based Test Design for Coherence Verification in 3D Caches

To provide high vertical interconnection density between device tiers, Through Silicon Via (TSV) offers a promising solution in 3D caches. It reduces the length of global interconnection and ensure...

CA based protocol processor for heterogeneous CMPs

In this work we propose a design approach for the Protocol Processor (PP) to determine the state of a data block accurately in a heterogeneous Chip Multiprocessors (CMPs) where different cores may follow separate cache coherence protocols. For the proposed design, we consider the cellular automata (CA) modelling tool invented by von Neumann in 1950s. The structural regularity and modularity of CA makes the design highly scalable and robust. The CA based PP while computing the states of a data block on read/write operation, can capture defects, if any, and there by realizes a fault tolerant PP without introduction of additional hardware logic.