Biplab K. Sikdar

Modular Design of testable reversible ALU by QCA multiplexer with increase in programmability

The quantum-dot cellular automata have emerged as one of the potential computational fabrics for the emerging nanocomputing systems due to their ultra-high speed and integration density. On the other hand, reversible computing promises low power consuming circuits by nullifying the energy dissipation during the computation. This work targets the design of a reversible arithmetic logic unit (RALU) in the quantum-dot cellular automata (QCA) framework. The design is based on the reversible multiplexer (RM) synthesized by compact 2:1 QCA multiplexers introduced in this paper. The proposed reversible multiplexer is able to achieve 100% fault tolerance in the presence of single missing or additional cell defects in QCA layout. Furthermore, the advantage of modular design of reversible multiplexer is shown by its application in synthesizing the RALU with separate reversible arithmetic unit (RAU) and reversible logic unit (RLU). The RALU circuit can be tested for classical unidirectional stuck-at faults using the constant variable used in this design. The experimentation establishes that the proposed RALU outperforms the conventional reversible ALU in terms of programming flexibility and testability. HighlightsA reversible QCA multiplexer logic (RM) is designed from irreversible multiplexer.Results show the effectiveness of the design in terms of cost and testing overhead.Fault testing capability is reported.A complete testable reversible arithmetic logic unit (RALU) is synthesized based on separate module of RAU and RLU.Reliability issue is addressed with modularity.

Realizing Reversible Computing in QCA Framework Resulting in Efficient Design of Testable ALU

Reversible logic is emerging as a prospective logic design style for implementing ultra-low-power VLSI circuits. It promises low-power consuming circuits by nullifying the energy dissipation in irreversible logic. On the other hand, as a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises energy efficient digital design with high device density and high computing speed. The integration of reversible logic in QCA circuit is expected to be effective in addressing the issue of energy dissipation at nano scale regime. This work targets the design of reversible ALU (arithmetic logic unit) in QCA framework and proposes a new “Reversible QCA” (RQCA). The primary design focus is on optimizing the number of reversible gates, quantum cost and the garbage outputs that are the most important hindrances in realizing reversible logic. Besides optimization, the fault coverage capability of RQCA under missing/additional cell deposition defects is analysed. The scope of reversible logic is further outstretched by introducing a novel DFT (design for testability) architecture around the reversible ALU that reduces testing overhead. The performance of proposed ALU is evaluated, subjected to different faults, and is established to be more effective than the existing ALU.

An efficient multiplexer in quantum-dot cellular automata

Quantum-dot Cellular Automata (QCA) technology is considered as the alternative to state-of-the-art CMOS due to its extra low-power, extremely dense and high speed structures at nano-scale. This paper proposes a novel design of 2:1 multiplexer in QCA, targeting better area efficiency and reduced input to output delay.

Thresholding using Quantum-dot Cellular Automata

Quantum-dot Cellular Automata(QCA), a promising alternative to CMOS technology, can provide a powerful and efficient computing platform for image processing which has heavy computational requirements. Image thresholding is one such image processing technique that plays a significant role in applications of image segmentation for its intuitive properties and simplicity. This work proposes an efficient architecture to carry out thresholding in image processing. It is developed around QCA technology and provides significant improvement over the existing approach.

Towards the hierarchical design of multilayer QCA logic circuit

Abstract As a potential alternative to CMOS technology, Quantum-dot Cellular Automata (QCA) promises efficient digital design with high device density and low power dissipation in the future. This work targets the development of multi-layered architecture in the QCA framework with the goal to build an efficient methodology for QCA based digital logic design. A strategy for modelling, digital devices around QCA multiplexer is framed, which directs to the conception of complex digital circuits with high device density and low latency (i.e., more quick functioning). The proposed multilayer design also points to inherent aspects of radius of effect of QCA cells and the layer spacing in multilayer architecture. Minimum clock zone (2 clock) with high compaction (0.01xa0μm 2 ) is achieved for the multiplexer designed in QCA framework. A heuristic approach to synthesize multilayer synchronized QCA logic circuit is also proposed. Experimental results illustrate significant improvements in design level in terms of circuit area, cell count and clock over that of conventional design approaches.

Design of universal logic gate targeting minimum wire-crossings in QCA logic circuit

Wire crossings limit the performance of a logic circuit in Quantum-Dot Cellular Automata (QCA) based design. Minimization of wire-crossings is, therefore, of prime importance in the current nanotechnology, susceptible to high error rates. This work proposes a QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The experimental designs establish that the UQCALG can lead to the cost effective design of QCA logic circuits that may not be possible with conventional ULG (Universal Logic Gate).

Synthesis of reversible universal QCA gate structure for energy efficient digital design

Quantum-dot Cellular Automata (QCA), a promising alternative to the current CMOS technology, can be a viable solution of thousands of cores in a chip in near future due to its very high device density of 1012device/cm2 and switching speeds of 10ps. On the other hand, the reversible logic is a promising computing paradigm in low power CMOS design, quantum computing, nanotechnology, and optical computing. Again, QCA consume low power which promises the energy efficient design of the logic circuits. However, the requirements of excessive logic gates and undesirable garbage outputs, while realising a function, limit the performance of a QCA based design. This work proposes a novel approach to synthesis a reversible universal QCA logic gate (RUG) structure with the target to reduce the garbage outputs as well as the logic gates of a design. This design addresses the fundamental issues of realizing reversible gates in nanotechnology and also its reliability and performance trade-off. The experimental designs establish that the RUG can ensure an energy saving, cost effective realization of QCA logic circuits that may not be possible with the conventional reversible logic gates.

A study on defect tolerance of tiles implementing universal gate functions

Quantum-dot cellular automata (QCA) are considered as the future alternative to state-of-the- art CMOS designs. The tile structures for the QCA circuit elements are proposed to enable effective modular design. This work introduces 3times3 tile structures for realizing the NNI (nand-nor-inverter) as well as the AOI (and-or-inverter) logic. The defect characterizations for such tiles are carried out to comment on the stability of designs. It analyzes the effect of cell deposition as well as the cell misplacement defects. The study on defective tiles point to the fact that the NNI tile is more defect tolerant than AOI under deposition defects. However, an AOI tile is comparatively less sensitive to misplacement of input/output. It is further noted that the AOI tiles display better detectability of multiple cell deposition defects than that of an NNI tile.

Design of reliable universal QCA logic in the presence of cell deposition defect

ABSTRACT The emergence of Quantum-dot Cellular Automata (QCA) has resulted in being identified as a promising alternative to the currently prevailing techniques of very large scale integration. QCA can provide low-power nanocircuit with high device density. Keeping aside the profound acceptance of QCA, the challenge that it is facing can be quoted as susceptibility to high error rate. The work produced in this article aims towards the design of a reliable universal logic gate (r-ULG) in QCA (r-ULG along with the single clock zone and r-ULG-II along with multiple clock zones). The design would include hybrid orientation of cells that would realise majority and minority, functions and high fault tolerance simultaneously. The characterisation of the defective behaviour of r-ULGs under different kinds of cell deposition defects is investigated. The outcomes of the investigation provide an indication that the proposed r-ULG provides a fault tolerance of 75% under single clock zone and a fault tolerance of 100% under dual clock zones. The high functional aspects of r-ULGs in the implementation of different logic functions successfully under cell deposition defects are affirmed by the experimental results. The high-level logic around the multiplexer is synthesised, which helps to extend the design capability to the higher-level circuit synthesis.

Multilayer design of QCA multiplexer

This work targets the design of a multiplexer in multilayer QCA (Quantum-dot Cellular Automata) framework. The proposed multiplexer satisfies the requirement of high device density as well as computing power. The impact of different design constraints, such as layer spacing, radius of induced effect and the size of QCA cell on logic synthesis in multilayer environment are thoroughly investigated. High level synthesis of digital design using the proposed multiplexer is explored that establishes the significant improvement in digital design with the layered structure over that of conventional design approaches.