Mamata Dalui

Fault Tolerant QCA Logic Design With Coupled Majority-Minority Gate

Synthesis of efficient DFT (Design for Testability) logic is of prime importance in robustly testable design of QCA based logic circuits. An ingenious universal QCA gate structure, Coupled Majority-Minority (CMVMIN) gate, realizes majority and minority functions simultaneously in its 2-outputs. This device enables area saving implementation of complex QCA logic. In the current work, we investigate cost effective DFT for QCA designs realized with CMVMIN. The fault effects at the gate outputs due to cell deposition and cell misplacement defects are characterized for concurrent testable circuit design. The effective use of unutilized outputs of CMVMIN gates, realizing a circuit, leads to the proposed fault tolerant design that may not be possible with the conventional gate structures.

Characterization of CA rules for SACA targeting detection of faulty nodes in WSN

The single attractor cellular automata (SACA) is of prime interest in devising schemes for different applications specially in authentication and cryptography. The synthesis of SACA in linear/additive domain has been proposed in literature. This work reports characterization of such a special class of CA beyond linear domain. The characterization is based on the analysis of individual CA rule and its potential to form the single length cycle attractors (point states). The proposed characterization targets design of a CA based scheme for detection of faulty nodes in a wireless sensor network. It enables identification of faults even in multiple nodes with out major computation overhead.

Design of universal logic gate targeting minimum wire-crossings in QCA logic circuit

Wire crossings limit the performance of a logic circuit in Quantum-Dot Cellular Automata (QCA) based design. Minimization of wire-crossings is, therefore, of prime importance in the current nanotechnology, susceptible to high error rates. This work proposes a QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The experimental designs establish that the UQCALG can lead to the cost effective design of QCA logic circuits that may not be possible with conventional ULG (Universal Logic Gate).

Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit

This work proposes a testable QCA (Quantum-Dot Cellular Automata) logic gate (UQCALG) realizing the universal functions. The design of UQCALG is based on the Coupled Majority Minority (CMVMIN) QCA structure with the target to reduce wire crossings as well as the number of clock cycles required to operate a QCA circuit. The characterization of defects in such design leads to synthesis of a test block, realized with the majority and minority voters, that ensures the desired testability of a circuit. The experimental designs establish that the UQCALG can result in cost effective design of testable QCA logic circuits that may not be possible with conventional ULG (Universal Logic Gate).

A Cache System Design for CMPs with Built-In Coherence Verification

This work reports an effective design of cache system for Chip Multiprocessors CMPs. It introduces built-in logic for verification of cache coherence in CMPs realizing directory based protocol. It is developed around the cellular automata CA machine, invented by John von Neumann in the 1950s. A special class of CA referred to as single length cycle 2-attractor cellular automata TACA has been planted to detect the inconsistencies in cache line states of processors’ private caches. The TACA module captures coherence status of the CMPs’ cache system and memorizes any inconsistent recording of the cache line states during the processors’ reference to a memory block. Theory has been developed to empower a TACA to analyse the cache state updates and then to settle to an attractor state indicating quick decision on a faulty recording of cache line status. The introduction of segmentation of the CMPs’ processor pool ensures a better efficiency, in determining the inconsistencies, by reducing the number of computation steps in the verification logic. The hardware requirement for the verification logic points to the fact that the overhead of proposed coherence verification module is much lesser than that of the conventional verification units and is insignificant with respect to the cost involved in CMPs’ cache system.

A cellular automata based highly accurate memory test hardware realizing March C

This work reports a highly accurate test structure for high speed memories. The theoretical bases of the design are the March algorithm and cellular automata (CA) proposed by von Neumann in 1950s. Theory of 3 and 5-neighborhood CA, employed for the current application, has been developed to enhance the self-testability of memory test logic. The special class of single length cycle attractor cellular automata, introduced in this work, accepts status of each memory word and evaluates it to decide on the faults in the memory. The extension of CA neighborhood to 5 enables propagation of the effect of faults in memory or in the test logic to the error line of the test structure. This overcomes the inability of classical memory test hardware designed with the ex - or and or logic.

CA Based Scalable Protocol Processor for Chip Multiprocessors

The protocol processor (PP) is a key component of the cache coherence controller (CC) in a Chip Multiprocessors (CMPs) cache system. PP computes the state of a block on every transaction (read/write operation) on the block while maintaining cache coherence in CMPs. This work proposes a novel design approach for the PP which can cater to the pressing need for determining the state of a data block with high accuracy. It is developed around the modelling tool of cellular automata (CA) invented by von Neumann in 1950s. The inherent regular, modular, cascadable structure of CA ensures high scalability and robustness in exascale design solutions.

Design of directory based cache coherence protocol verification logic in CMPs around TACA

The conventional test schemes for Chip Multiprocessors (CMPs) are costly, time consuming and power hungry. This demands search for new test methodologies. In this work, we employ cellular automata (CA) to develop a high speed protocol verification logic for CMPs realizing directory based cache coherence system. A special class of CA referred to as single length cycle 2-attractor cellular automata (TACA), has been introduced to identify the inconsistencies in cache line states of processors private caches. The TACA theory is developed to realize low cost hardware of the design enabling quick decision on the cache coherency that is desirable for the CMPs.

Quick consensus through early disposal of faulty processes

This work reports an efficient solution for reaching agreement (consensus) among the processes of a distributed system. The better efficiency is achieved through early disposal of faulty processes while approaching for a consensus. The introduced network partitioning scheme further facilitates the progress by reducing the message exchange overhead. Simulation results establish that the proposed solution significantly reduces the message exchange complexity, in comparison to the schemes reported so far, simultaneously ensuring the fault-tolerance ability of a system as that of the known best results.

Design of coherence verification unit for CMPs realizing dragon protocol

The data coherence in Chip Multiprocessors (CMPs) cache system is to be more accurate and reliable. A system with single producer and multiple consumers uses update based coherence protocol (dragon). This work proposes an effective solution for coherence verification in dragon through introduction of highly efficient test logic (fault detection unit). The test design is based on the modular structure of Cellular Automata (CA). The SACA (single length cycle single attractor cellular automata) has been introduced to identify the inconsistencies in cache line states of dragon. The simple hardware implementation of the CA based design realizes quick decision on the cache coherency in CMPs with 100% accuracy.