Bidyut K. Bhattacharyya

Moisture absorption and mechanical performance of surface mountable plastic packages

The results of moisture-absorption tests on 68L plastic-leaded chip-carriers (PLCC) are presented. Environmental variables include both temperature (30, 40, 50, 60 and 85 degrees C) and relative humidity (24, 40, 60 and 85%). Control samples of pure molding compound were tested to determine the effect of leads on the PLCC samples. Comparison was made between absorbed moisture measurements and predictions based on the one-dimensional Fickian diffusion solution. Nonlinear regression analysis indicates that Fickian diffusion behavior represents the actual moisture absorption for relative humidities below 85%. At 85% RH, however, the deviation becomes significant after 500 hr. On the basis of the agreement at moderate values of relative humidity and time, analytical models were developed that show the effect of temperature and relative humidity on moisture mass gain and diffusion coefficient. A stress and deformation analysis was performed to predict the envelope in parameter space separating cracked and uncracked packages. The model used depends on the presence of saturated water between the die paddle and the molding compound. Doming of the plastic underneath the paddle is attributed to flashing of all the trapped liquid water to steam.<<ETX>>

A method of designing a group of bumps for C4 packages to maximize the number of bumps and minimize the number of package layers

In this paper we are going to show a method of defining a group of C4 bumps that can be placed in a repeated manner on silicon die. It is also shown that for a given package design guideline all these bumps can be routed in a given package layer. This method also allows one to route a maximum number of C4 bumps for a given number of package layers. These groups of bumps can be placed along the die edge, along the diagonals of the die, or both. This method is also verified by extensive experimental drawings on various die sizes, as well as for various package design guidelines. It is shown that this method takes the minimum distance from the die edge for the placement of the maximum number of bumps for a given package routing layer. If the numbers of I/Os are reasonable compared to the die size, then this design methodology can help one design a set of bond pads in the die that can be utilized both for C4 and for wire bond technology.<<ETX>>

Some properties of Nuclepore filters

We present the results of various measurements we have made to characterize Nuclepore filters. These include nitrogen and helium adsorption isotherms, heat capacity and SEM studies of pore size distribution and pore density.

High-performance PQFP

The design of a high-performance plastic quad flat back (PQFP) is described. It is a multilayer package designed to provide a high level of electrical and thermal performance. The design maintains the JEDEC standard package outline; the changes are internal to the plastic body of the PQFP. A pair of parallel metal planes is added to serve as the power and ground paths for the device. By replacing a substantial portion of the highly inductive leads by the plane and shorting all V/sub cc/ or V/sub ss/ leads through their respective planes the power-group loop inductance is reduced significantly. The planes increase the power-ground capacitance by approximately 500% while lowering the capacitive coupling between leads. The planes spread the heat generated by the IC chip over the total area of the package, reducing the package thermal resistance and eliminating the need for internal heats conductors.<<ETX>>

A Mathematical Technique to estimate the High Frequency Current Inside the Silicon Die from the Noise Measurements

In this paper, we have shown a method to determine the current drawn by the device as a function of time. It is normally difficult to determine the switching current drawn by the device as a function of time. In this paper, the current drawn by the device is determined by measuring the voltage (Vx) at some desire location on the top of the device and then by simulating the impedance profile from the basic topology of the power delivery network. The L, C and R of the power deliver network were assumed as the fundamental parameters of our methodology. In our methodology, some of the AC parameters of power delivery network including the average current drawn by the device, the average voltage at the measuring node and the steady power supply voltage, were assumed to be known.

Impact on inter symbol interference (ISI) noise due to simulation error

In this paper, we are going to discuss the error in determining the actual intersymbol interference noise (ISI) due to different circuit simulation methodology, while using a standard circuit simulator. In this paper, we have compared three different methods to predict accurately ISI noise. All three methods show that errors caused by circuit simulation can make the eye worst. We have also shown a method which allows one to determine that error and calculate the actual range of ISI noise. As we move towards sampling mVolt signals at the receiver end (Bhattacharyya, 2004 and Bhattacharyya, 2005), one needs to minimize the error that arises due to circuit simulation methodology. This is essential, in order to predict the actual performance of the interconnect.

Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment

Advancement in payment technologies has an important impact on ones quality of life. Emerging payment technologies create both opportunities and challenges for the future. Being a quick and convenient process, contactless payment gained momentum, especially with merchants, with throughput being the main parameter. However, it poses risks to issuers, as no robust customer verification method is available. Thus, efforts have been underway to evolve and sustain a well-organized, efficient, reliable, and secure unified payment system, which may contribute to the smooth functioning of the market by eliminating obstacles in business.

Reduction of Noise Using Continuously Changing Variable Clock and Clock Gating for IC Chips

The performance of silicon chip depends on the operating voltage of the chip. The chip should be designed using proper power and ground bond pads to minimize the power supply noise. When the chip starts working from the sleep mode, then the sudden rise in current inside the chip causes LdI/dt noise. This noise reduces the power supply voltage, which in turn reduces the operating frequency of the chip. This makes the chip manufacturer to sell products of high-performance chips at a lower operating frequency. In order to ramp this current slowly, an innovative and fundamentally new method is implemented. In this proposed method, we have increased the operating frequency inside the chip slowly (from fmin to fmax) to control the current ramp and at the same time performed clock gating (CG) to minimize noise by suppressing the current drawn by the device. We have applied this concept of variable frequency together with CG in a 3-b up counter to demonstrate that one can construct a design where the clock can be modulated during its functional operation without any functional failure.

Computer aided electrical modeling of VLSI packages

A software tool for modeling package parasitics and generating equivalent circuit files is described. This tool is a collection of software modules and generates SPICE-like netlists for single and multilayer packages (plastic/ceramic). The package parasitics are evaluated using geometry and material properties extracted directly from the existing CAD (computer-aided design) package database. Using this tool, the chip designer can model the combined device, package, and system environment. Results for modeled package parasitics are compared to experimental values, and results of simulations for noise generated on the i486 processor package ground plane due to simultaneously switching signal lines driving a system load are presented.<<ETX>>

Method to Simulate Rise Time of Current Drawn by a Microprocessor

We have developed a new method to simulate the effective rise time of current drawn by each cell in a microprocessor so that the total noise is consistent with values measured at the power and ground reference points inside the die. Normally, the measured values are much smaller than simulated values. In this paper, several exponential functions with varying time constants are staggered and combined at different starting time values to generate the effective current profile which was used for noise estimation. The model utilizes a realistic jitter-based distribution function compared to a step function used in existing models for the initial small amount of saturated current ramp. The practical model developed in this paper is useful for optimizing the cost and performance of microprocessors.