Bill Yang Liu

Integrated stereo /spl Delta//spl Sigma/ class D amplifier

A 2/spl times/40 W class D amplifier chip is realized in 0.6-/spl mu/m BCDMOS technology, integrating two delta-sigma (/spl Delta//spl Sigma/) modulators and two full H-bridge switching output stages. Analog feedback from H-bridge outputs helps achieve 67-dB power supply rejection ratio, 0.001% total harmonic distortion, and 104-dB dynamic range. The modulator clock rate is 6 MHz, but dynamically adjusted quantizer hysteresis reduces output data rate to 450 kHz, helping achieve 88% power efficiency. At AM radio frequencies, the modulator output spectrum contains a single peak, but is otherwise tone-free, unlike conventional pulse-width modulation (PWM) modulators which contain energetic tones at harmonics of the PWM clock frequency.

Integrated stereo delta-sigma class D amplifier

A 2/spl times/40W (into 4/spl Omega/ with a 20V supply) integrated stereo /spl Delta//spl Sigma/ class D amplifier with 100dB SNR is realized in a 0.6 /spl mu/m CMOS process with DMOS transistors and buried Zener diodes. Feedback from power stage outputs gives 0.001% THD and 65dB PSRR. The modulator clock rate is 6MHz, but dynamically adjusted quantizer hysteresis reduces the output data rate to 450kHz, helping achieve 88% efficiency.

Filterless multi-level delta-sigma class-D amplifier for portable applications

A 2W filterless class-D amplifier using multi-level delta-sigma modulation is presented. LC filters consume large PCB space and add significant system cost, so filterless class-D solutions are preferred for portable applications. In this design, a multi-level, delta-sigma modulator is implemented to achieve high efficiency and high performance without the use of a filter. Although the modulator internally generates an 8MHz clock, the average switching frequency of output signal is dynamically reduced to 300kHz to minimize switching loss. Analog feedback from the output stages along with common-mode control yields 0.003% total harmonic distortion, and 103dB dynamic range.

Improved on-chip components for integrated DC-DC converters in 0.13 µm CMOS

A fully-integrated DC-DC converter with on-chip inductors and capacitors is realized in a 0.13 µm CMOS technology. By using an asymmetric, high-Q inductor, power efficiency comparable to that of converters implemented with off-chip inductors is achieved. Straightforward analysis of high-density capacitor structure results in minimal ESR and optimal filtering of the output. The manufactured converter achieves a peak power efficiency of 80.5 % for an optimal load current of 170 mA and a voltage conversion ratio of 0.76 when switching at 180 MHz. This design is approximately 23 % more efficient than a linear regulator at a voltage conversion ratio of 0.55. A simple voltage mode PWM control keeps the output stable at the desired level, under load conditions from 0 mW to 720 mW.

On-Chip Compensated Wide Output Range Boost Converter with Fixed-Frequency Adaptive Off-Time Control for LED Driver Applications

An on-chip compensated wide output range boost converter with fixed-frequency adaptive off-time current-mode control is presented. The small signal characteristic of the boost converter with current-mode control is reviewed, and an adaptive current sensing technique is proposed to reduce the variation of phase margin at different output voltages. On-chip compensation is achieved with a Type II compensator. Adaptive off-time control is adopted for its fast response and no need for slope compensation, while its disadvantage of varying switching frequency is eliminated by the proposed off-time generator. The IC controller was fabricated in a 0.5 μm 2P3M BCD 40 V process. Measurement results confirm that an output range of 5.5 V ~ 36 V with an input voltage of 5 V is achieved. The switching frequency is fixed at 1 MHz with a variation of ±1%. The measured peak efficiency and maximum output power are 92.9% and 8.6 W, respectively. For a load step of 200 mA using a 3.3-μH inductor and a 20-μF output capacitor, overshoot and undershoot of the load transient responses are smaller than 1% of the output voltage.

A constant off-time controlled boost converter with adaptive current sensing technique

Using adaptive current sensing (ACS) technique, a constant off-time controlled boost converter with an improved off-time generator (OTG) is presented. With the ACS technique, this boost converter achieves wide conversion range operation without external compensation circuits. An improved OTG is proposed to compensate the switching frequency variation. The converter has been implemented in 0.5um 40V BCD process. Measurement results show that a conversion range of 5V input to 5.5~36V output and switching frequency variation of 1% can be obtained. The overshoot or undershoot in different conversion ratios is only about 0.5% of the output voltage with a load current step of 200mA.

An 80% peak efficiency, 0.84mW sleep power consumption, fully-integrated DC-DC converter with buck/LDO mode control

A fully-integrated step-down DC-DC converter with LDO mode to reduce the sleep power consumption and improve efficiency at light loads is presented. The converter can switch adaptively between the buck converter and the LDO mode by continuously sensing the load current. Besides, lossless current sense technique is implemented for the mode selection circuits. An improved LDO is also proposed to achieve good stability under various loads. The chip was implemented in 0.13µm CMOS technology. The measured peak efficiency reaches 80% at 90mA load, and efficiency at 10mA load increases by 22.6% compared with forced buck converter mode. Furthermore, the overall power consumption is reduced by 12X at the sleep mode, from 10mW without the hybrid mode to 0.84mW.

Power optimization of high performance ΔΣ modulators for portable measurement applications

This paper, power optimization of two high performance ΔΣ modulators for portable measurement applications is presented. One modulator is a single-loop single-bit topology which achieves an 89.8dB peak SNDR and consumes 20μW with a 1.5V supply. Here, a new power efficient current mirror Class-AB OTA is introduced to reduce the power. The other modulator adopts both multi-bit technique and switched-opamp (SO) technique to realize the ultra-low power target. Its total power consumption is only 9μW at a 1.8V supply, and the peak SNDR reaches 80.5dB. Especially, a new fully-clocked SO is proposed in this modulator to achieve a 50% power saving and double Figure-of-Merit (FOM) over the traditional type. Besides, to realize a zero-optimization coefficient of 1/100 and improve the performance, a novel resonator idea applicable to SO technique is adopted with 75% power and 70% area reduction. Both modulators are fabricated in a low cost 0.35μm CMOS process with a bandwidth of 1 kHz. The measured results show high FOM of the designed modulators.

A dual-path, current-sensing resistor-free boost LED driver with fast PWM dimming

A boost LED driver features high PWM dimming ratio and optimized efficiency is presented. This LED driver, which having low dropout voltage and is able to drive 3~7 LEDs in series with constant output current and fast PWM dimming, is alternative for brightness adjustment. A dual-path control scheme with automatically state switching and maintenance is proposed. Meanwhile, a cascode current mirror structure is adopted with the output transistor multiplexed as LED PWM dimming transistor. Implemented in 0.5um 25V BCD process, the measurement results show that a voltage conversion range of 5V input to 6~21V output with constant output current is achieved. With automatically switching dual-path control and optimized current mirror, the response time during PWM dimming is reduced to as less as 240ns and the efficiency is kept above 89% over wide PWM dimming ratio @250mA output current.

Ultra low-FOM high-precision ΔΣ modulators with fully-clocked SO and zero static power quantizers

In this paper, two high-precision switched-opamp (SO) based ΔΣ modulators with ultra low figure-of-merit (FOM) are introduced respectively for bio-medical and audio applications. To save 50% power, both modulators adopt novel fully-clocked current mirror SOs with new bias circuits especially designed for SO. Besides, several measures are proposed separately in two modulators to ensure high performances. Both circuitries are implemented in 0.18µm CMOS. The modulator-I, for bio-medical applications, employs high density MOSCAPs to reduce chip area. Also, an innovative zero static power quantizer using MOSCAP-strings is developed to save up to 96% power and 69% area than traditional structure. With only 13µW power consumption at 1.0V supply voltage, it achieves 85dB peak-SNDR, 44.7fJ/conv.-step FOM for 10 kHz bandwidth. In the modulator-II, for audio applications, a novel 17-level scheme consisting of only nine comparators and two capacitor-strings is introduced to remove static power completely and save 40% chip area over the traditional quantizer. In addition, a dual cycle shift (DCS) DWA technique is introduced here to suppress in-band tone effectively. The modulator-II achieves 92dB peak-SNDR and 35.6fJ/conv.-step FOM with only 58µW power consumption at 0.9V supply voltage.