Bingcai Sui

Nano-Reconfigurable Cells With Hybrid Circuits of Single-Electron Transistors and MOSFETs

We propose and numerically analyze three novel reconfigurable logic cells (reconfigurable NAND/NOR, NAND/XNOR, and XNOR/XOR cells) based on single-electron transistor (SET) and MOSFET hybrid circuits. These reconfigurable cells can work normally at room temperature with high flexibility and performance. Compared with pure MOSFET circuits, the cells proposed in this paper can flexibly realize many more functions with high performance at much lower costs of area and power. Additionally, compared with pure SET circuits, the hybrid SET/MOSFET circuits can achieve higher voltage swing. Finally, the reconfigurable logic cells consisting of SETs and MOSFETs are very useful for the very large scale integration based on SETs.

Analysis of negative differential conductance of single-island single-electron transistors owing to Coulomb oscillations

Despite many years of effort, the precise origin of negative differential resistance (NDR) shown by some organic layers remains unclear. Tang et al. accounted qualitatively for NDR phenomena by coulomb blockade of single-electron transistors (SETs). From this foundation, a novel method based on analysis of the charge stability diagram of a SET is proposed in this study. The method can be used to systematically analyse negative differential conductance (NDC) characteristic of a SET and some organic layers. With this method, the NDC effect is explained with respect to device parameters, and several NDC cells proposed by others are analysed in detail. The results show that this method can be efficiently used to analyse the NDC effect of SETs and some organic layers.

A compact analytical model for multi-island single electron transistors

Multi-island single electron transistor (SET) has become a promising candidate for the kernel device of the logic circuit in the near future. A novel compact analytical model for multi-island SET is proposed in terms of current. The new approach is based on the orthodox theory of single electron tunnelling and steady-state master equation. The model is accurate and fast compared with SIMON, and suitable for the ASIC design of multi-island SET circuit simulation.1

Reconfigurable single-electron transistor logic gates

Single-electron transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. And many researchers have proposed many logic units based on SETs. Through the analysis and simulation of the body-voltage effect of SET, for the first time, we propose a reconfigurable SET logic gate (RSETLG) based on the control of body-voltage. The simulation result by SPICE shows that the RSETLG can be very powerfully used to design many different logic gates because of its simple structure.

Reconfigurable pseudo-NMOS-like logic with hybrid MOS and single-electron transistors

A novel reconfigurable hybrid single electron transistor/MOSFET (SETMOS) circuit architecture, namely, reconfigurable pseudo-NMOS-like logic is proposed. Based on the hybrid SETMOS inverter/buffer circuit cell, reconfigurable pseudo-NMOS-like logics that can work normally at room temperature are constructed. This kind of reconfigurable logic can implement up to 2n sorts of functions at n inputs with different configurations. It only consumes 1 PMOS transistor, 1 NMOS transistor and n SETs, which reduces logic-gate density and power consumption significantly.

A Full Adder Based on Hybrid Single-Electron Transistors and MOSFETs at Room Temperature

A full adder based on hybrid single-electron transistors (SET) and MOSFETs (SETMOS) at room temperature is proposed in this paper. Because the SET can play the same role as compensatory MOSFETs, we design a fuller adder with hybrid SETMOS. Further more, we simulate the logic element by HSPIC and the simulation result shows that the logic element implements the function of a full adder. To compare our work with conventional CMOS logics, which significantly reduces area and power consumption.

Analysis and applications of NDR characteristics in single-electron transistor

Single Electron Tunneling Transistors (SETs) are promising for very large scale integrated circuits due to their ultra-low power consumption and ultra-small feature size scalability. Devices with NDR characteristics are very useful to be used to design amplifier, oscillation, memory and so on. As a three-port device, NDR characteristics of SET is very useful for VLSI. We analyse several NDR cells based on SETs mostly focused on recently. All the cells use coulomb oscillation to produce NDR characteristics, which can be used to design SRAM, multiple-valued logics, and so on. Therefore, it is very valuable to make research on the NDR characteristics of SETs.

Validation and analysis of negative differential resistance of single-electron transistor with conductance model

Despite many years of effort, the precise mechanism of negative differential resistance (NDR) of single-electron transistor (SET) remains unclear, and this lack of knowledge has become a major obstacle in the research and development of new electronic devices to make use this effect. This paper proposes a conductance model to validate and analysis NDR of SET, which is based on the classical orthodox theory of single electron and obtained by analyzing the source of the single-electron transistor leakage conductance, and carried out a detailed analysis and discussion. The source of leakage conductance of the SET with the source-drain voltage changes occur periodic oscillation attenuation and gradually converge to the intrinsic conductivity values with the increase of the source-drain voltage, and the NDR effect can be attributed to Coulomb blockade. It is showed from the results that this method can be used to validate and preliminary explain the NDR effect of SET.

A model for energy quantization of single-electron transistor below 10nm

Single-electronic transistor (SET) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. Along with the size of coulomb island become smaller and smaller, the energy quantization of single electron transistor based on charge state come forth and from obviously to more obviously. A qualitative analysis to single-electron transistors base on charge state with discrete energy levels, is introduced in this paper. Compared with other analysis to single-electron transistor based on charge state without discrete energy levels, our result is close to fact. Through the comparison, it can be get that the former is accurate and close to fact compared with the simulator without discrete energy levels, and is very useful for the ASIC design of SET devices.

Reconfigurable logic gate implemented by suspended-gate single-electron transistors

As the most attractive candidates for post-CMOS era, single-electronic transistors (SETs) can potentially deliver high device density and power efficiency at good speed. SET with suspended-gate has many more unique merits. Reconfigurable logic gate based on suspended-gate SET is designed, which can efficiently make use of the tunable coulomb oscillation and NEMS gate capacitances. The simulation result shows that the reconfigurable cell based on suspended-gate SET can flexibly realize many more functions at room temperature with high performance at much lower cost of area and power, and be very useful for the logic design based on suspended-gate SETs to construct some more efficient structures(e.g. FPGA, programmable architecture, and so on).