Yaqing Chi

Heavy-Ion-Induced Charge Sharing Measurement With a Novel Uniform Vertical Inverter Chains (UniVIC) SEMT Test Structure

In this paper, a novel uniform vertical inverter chains (UniVIC) single event multiple transient (SEMT) test structure is proposed for the first time. Charge sharing between standard inverters is measured for the first time experimentally. The heavy-ion experiment results in 65 nm bulk CMOS process indicate that charge sharing can impact three transistors at most. At the same time, the occurring probability of charge sharing is attained for the first time experimentally. 3D TCAD simulations have also verified them. In total, the conclusions are helpful for researchers to have a direct knowledge of charge sharing in concrete circuits, and then to improve the precise of soft error evaluation.

Characterization of Single-Event Transient Pulse Broadening Effect in 65 nm Bulk Inverter Chains Using Heavy Ion Microbeam

The propagation induced pulse broadening (PIPB) effect of the SET pulses in 65nm bulk inverter chains is characterized and discussed generated by the heavy ion microbeam. An odd-even separated layout placement strategy is implemented in the test chip to improve the resolution of the broadened width measurement. The experiment results show that bigger transistor size is able to inhibit the PIPB effect better, but the well structure and layout topology show insignificant influence on the PIPB effect of the SET pulses generated by the low LET heavy ions.

Radiation hardness evaluation of the YHFT-DV digital signal processor

The Total Ionizing Dose and Single Event Effects test results of YHFT-DV, a 32-bit floating-point digital signal processor are reported in this paper. The result shows the DSP is well radiation hardened.

Comparison of single-event upset generated by heavy ion and pulsed laser

Single-event upset (SEU) is investigated using heavy ion and pulsed laser. The measured SEU cross sections of D and DICE flip-flops are compared. Measurement results indicate pulsed laser is capable of inducing similar SEU to those induced by heavy ion. 3D-TCAD simulation is performed to investigate the factors to impact pulsed laser induced SEU. Simulation results show that the beam spot size significantly impacts SEU cross sections in both low and high laser energy while the variation of the equivalent LET only impacts SEU cross sections in the low laser energy.

Modeling the impact of process and operation variations on the soft error rate of digital circuits

Dear editor, Process or operation variations are important factors in the soft error rate (SER) of integrated circuits [1, 2]. During manufacturing or other operations, inevitable process or operation variations lead to changes in the electrical parameters of transistors, which can result in sizeable shifts in the SER of integrated circuits [3]. Some studies have reported that the hardness of test chips can vary by more than 20% as a result of process or operation variations [4]. Therefore, it is vital to account for process and operation variations when evaluating the circuit sensitivity and predicting the SER in advanced CMOS technology. In previous research, some models for evaluating the circuit sensitivity caused by process or operation variations have been derived. For instance, Mostafa et al. [5] proposed a critical charge model to evaluate the single-event upset (SEU) sensitivity of static random access memorys (SRAMs) and flip-flops. Based on this model, the critical charge was determined by the driving current of the transistors. Process or operation variations affected this driving current, leading to changes in the calculated critical charge. Recently, Monte Carlo simulation approach has been used to evaluate the circuit sensitivity [6]. This approach shifts the device parameters to model process or operation variations. A current source, which is represented as the ion induced transient current, was implemented in the circuit node. The circuit response was simulated by circuit-level simulation tools based on the variational device parameters. Although these models or approaches have been used to evaluate the circuit sensitivity caused by process or operation variations, they still have some limitations. For instance, the critical charge model is strongly dependent on the circuit topology. Different circuit topologies result in different equations to calculate the critical charge. Moreover, some process parameters, such as mobility, affect the driving current slightly. However, they have a significant effect on the collected charge of sensitive transistors. Although the calculated critical charge does not change, these process parameters also affect the circuit sensitivity and lead to SER variations. Therefore, we propose a circuit-level simulation approach to evaluate processor operationinduced SER variations, as shown in Figure 1. Our approach consists of three interacting components. The first component uses a Monte Carlo simulation to determine ion transportation and calculate the ionized charge in the semiconductor. In the second component, circuit-level charge collection models calculate transient currents after ion strikes. In this component, a novel model is used to determine the parameters affected by process or

Experimental characterization of the dominant multiple nodes charge collection mechanism in metal oxide-semiconductor transistors

We propose an experimental method to investigate the dominant multiple node charge collection mechanism. A transistor array-based test structure is used to distinguish charge collection owing to the drift-diffusion and parasitic bipolar amplification effect. Heavy ion experimental results confirm that drift-diffusion dominates multiple node charge collection at low linear energy transfer (LET). However, the parasitic bipolar amplification effect dominates it at high LET. We also propose simple equations to determine the critical LET which may change the dominant multiple node charge collection mechanism. The calculated LET value is consistent with the heavy ion experimental results.

A Scan Chain Based SEU Test Method for Microprocessors

A test method based on the scan chain technique is proposed to evaluate the single event upset performance for all the flip-flops in the microprocessors. The single event upset (SEU) performance of a digital signal processor is evaluated using the proposed method and program test method with different working frequencies. Heavy ion irradiation experiment results show that this method is able to capture all the SEUs in the whole chip with no escape and has few infections from the single event transients, which is helpful to study the SEUs precisely in the complicated processors.