Hailiang Zhou

Performance Optimization of MOS-Like Carbon Nanotube FETs With Realistic Contacts

To make an exact research into the performance of conventional MOS-like carbon nanotube field-effect transistors (C-CNFETs) with realistic contacts, we studied the effect of Schottky contacts on the performance of C-CNFETs following a detailed analysis of contacting circumstances of C-CNFETs in circuit applications. As the research results show, conventional C-CNFETs suffer from weak subthreshold and off -state performances due to the band-to-band tunneling of holes even with Schottky contacts taken into account. Consequently, device structures based on three novel strategies, viz., an electrostatic doping strategy, a dual-gate-material strategy, and a staircase doping strategy, have been proposed. In addition, the simulation results reveal that these three device structures can improve the device performance of C-CNFETs in the form of steeper subthreshold characteristic, low enough potential off-state current, or (and) monotonic transfer characteristic. At the same time, it should be noted that the performances of these three strategies sensitively depend on the choice of tuning voltage, work function of gate material, or doping concentration of lightly doped source/drain leads, which should be paid with much attention in application.

Performance optimization of MOS-like carbon nanotube-FETs with realistic source/drain contacts based on electrostatic doping

Due to carrier band-to-band-tunneling (BTBT) through channel-source/drain contacts, conventional MOS-like Carbon Nanotube Field Effect Transistors (C-CNFETs) suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Greens function (NEGF) formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold performance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.

A compact analytical model for multi-island single electron transistors

Multi-island single electron transistor (SET) has become a promising candidate for the kernel device of the logic circuit in the near future. A novel compact analytical model for multi-island SET is proposed in terms of current. The new approach is based on the orthodox theory of single electron tunnelling and steady-state master equation. The model is accurate and fast compared with SIMON, and suitable for the ASIC design of multi-island SET circuit simulation.1

Reconfigurable single-electron transistor logic gates

Single-electron transistors (SETs) are considered as the attractive candidates for post-COMS VLSI due to their ultra-small size and low power consumption. And many researchers have proposed many logic units based on SETs. Through the analysis and simulation of the body-voltage effect of SET, for the first time, we propose a reconfigurable SET logic gate (RSETLG) based on the control of body-voltage. The simulation result by SPICE shows that the RSETLG can be very powerfully used to design many different logic gates because of its simple structure.

Challenges from quantum capacitance in process of high performance carbon nanotube-FETs design

Due to effective elimination of carriers band-to-band tunneling through channel-source/drain interface, Dual-Gate-Material MOS-like Carbon Nanotube Field Effect Transistors (DGMC-CNFETs), proposed by our research group previously, can not only increase the ON-OFF current ratio, tune sub-threshold voltage, decrease device power, but also eliminate the ambipolar transporting property effectively. However, as a typical low-dimension system, DGMC-CNFETs suffer from effects of quantum capacitance inevitably. The effect of quantum capacitance on device band profile and thus the transporting characteristic is studied. Simulation results show that quantum capacitance can not only result in a great increase of OFF current, but also prevent sub-threshold swing from decreasing with the increase of insulator capacitance. Whats more important is that, due to the appearance of band-to-band tunneling at gate electrode-tuning electrode interface, quantum capacitance can even destroy the unipolar transporting property of this novel device design, which would have a negative impact on its application in circuits. At last, several suggestions are given to reduce the effects of quantum capacitance on the performance of DGMC-CNFETs.

Effect of quantum capacitance on switching speed in T-CNFETs

The effect of quantum capacitance (QC) on the switching speed in T-CNFETs (Tunneling Carbon Nanotube Field Effect Transistors) is investigated with simulation using NEGF (Non-Equilibrium Greens Function) formalism. Firstly, based on the analytical expression of SS, a quantitative study of the source/drain leads doping level is made to obtain an averaged inverse subthreshold slope(SS) as small as possible. And then the impact of QC on the gate control, thus on SS, is studied. Lastly, for the first time, approaches for restricting the impacts of QC are investigated, such as tuning the drain-source bias condition or CNT diameter which are governed by the analytical expression presented at the end of this paper. The modeling results reveal that the QC in T-CNFET has a negative impact on both the SS and on-current, and such impact could be restricted effectively with a proper choice of drain-source voltage and CNT chirality.

Performance Optimization of Conventional MOS-Like Carbon Nanotube-FETs Based on Dual-Gate-Material

Due to carriers Band-To-Band-Tunneling (BTBT) through channel-source/drain contacts, Conventional MOS-like Carbon Nanotube Field Effect Transistors (C-CNFETs) suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device design based on dual gate material is proposed. The simulation results show that, with proper choice of tuning gate material, this device design can not only reduce the ambipolar conductance and increase the available ON-OFF current ratio but also decrease the average sub-threshold swing, which are all very desirable in circuit design to reduce the system power and improve the working frequency as well. Further study reveals the fact that the performance of the proposed design depends highly on the choice of tuning gate material which should be paid with much attention in application.

Opitimization of tunneling carbon nanotube-FETs based on stair-case doping strategy

Due to the fact that either holes or electrons can band-to-band-tunnel (BTBT) through channelsource/drain contacts, tunneling carbon nanotube field effect transistors (T-CNFETs) suffer from ambipolar transporting characteristic. To suppress such ambipolar conductance, a novel device design based on stair-case doping strategy of drain region is proposed first in this paper. The dependences of available ON-OFF current ratio, practical ON-OFF current ratio with certain gate bias range and the average sub-threshold swing on the doping level of drain region are studied. Simulation results show that such device design can not only increase the ON-OFF current ratio largely but also result in a clear decrease of sub-threshold swing. At the same time, however, such stair-case doping strategy would broaden the depletion region and result in an increase of device area cost. Particular attention should be paid to the choice of doping level of drain region to make a proper tradeoff between power, speed and area in application.