Binjie Ge

An UHF RFID transponder with novel demodulator and security algorithm

An UHF Radio Frequency Identification (RFID) transponder, which can function according to either standard ISO 18000–6B or security ISO 18000–6B with Advanced Encryption Standard (AES), is presented in this paper. The UHF RFID transponder is composed of analog front-end (AFE) and digital signal processing unit. A novel demodulator in AFE is presented in this paper. Silicon area occupied by the demodulator is only 21% of traditional structure and it could demodulate input signal with data rate ranging from 10Kbps to 870Kbps. In digital processing unit, 128-bit AES algorithm is built in to ensure security communication between transponder and reader. Total chip area without test pads is 0.7mm2@0.18µm CMOS process and consumes 15µW without writing Memory.

An UHF RFID transponder for ISO 18000-6B

An UHF Radio Frequency Identification (RFID) transponder complying with Chinese UHF RFID band setting is presented in this paper. The RFID transponder is composed of analog-RF front-end and digital signal processing unit. The analog-RF front-end is mainly made up of voltage multiplier, limiter, power-on-reset (POR), clock generator, demodulator and modulator. This work proposes a novel clock generating scheme with features of area effective and high precision which uses ring oscillator and counter, accompanying preamble sent by reader before data communication. Clock generator drives transponder with clock variation less than ± 1.76% which is below ±15% requested by standard. Besides, a new demodulator is presented in this paper. Silicon area of demodulator is only 21% of traditional structure and it could demodulate input signal with data rate ranging from 10Kbps to 870Kbps. Full chip area without test pads is 0.7mm2@0.18um CMOS process and consumes 15uW without Memory.

A mobile UHF RFID reader with high linearity receiver

A Mobile UHF RFID Reader made up of RF frontend, phase lock loop, analog baseband and digital baseband is designed and implemented in a 0.18um CMOS process. A RX configuration without LNA is adopted in this design for high linearity purpose. The 1dB input compression point is over 2dBm and input return loss is better than −10dB from 840MHz to 930MHz. A novel servo loop based DC offset cancellation scheme is realized without off-chip component. The reader consumes a power of 420mW with 20dBm power output. The sensitivity reaches to −71dBm. The whole chip occupies 3mmX3.7mm in 0.18um CMOS process.

Design and implementation of a novel programmable power monitor chip

This paper proposes a novel programmable power monitor chip. With only three program pins and without any off-chip devices, the chip has 36-program states by taking different connections for the 3-program pins. The chip can monitor the voltage from 1.5v to 5.0v with 0.1v step. Special SH circuit and current limited digital blocks are employed to achieve ultra low quiescent power. The implementation is based on 2M1P 0.5um mixed signal process, the die area is 0.24mm2, and the quiescent current is only 3uA.