Kwon-Shik Park

A Novel Level Shifter Employing IGZO TFT

A new level shifter employing indium-gallium-zinc-oxide thin-film transistor (IGZO TFT) for a display panel was proposed and successfully fabricated. Two clock signals with 180° out of phase and a discharging TFT were employed to obtain a full-swing output. The IGZO level shifter has successfully exhibited a wide swing output from VDD to VSS without any additional power sources and input signals. The power consumption is 0.30 mW at a clock frequency of 12.5 kHz. The proposed level shifter with a depletion-mode device would be an important building block for an oxide TFT display.

Comparison of Top-Gate and Bottom-Gate Amorphous InGaZnO Thin-Film Transistors With the Same SiO 2 /a-InGaZnO/SiO 2 Stack

We demonstrate top-gate and bottom-gate structures of amorphous indium-gallium-zinc-oxide thin-film transistors and compare their device operation. A replica material stack is fabricated for depth profile characterization to correlate with device results. We mainly focus on the oxygen content at the top and bottom. Key process factors that affect device reliability are determined based on material analysis, subgap density-of-states extraction by monochromatic photonic capacitance-voltage technique, and device simulations. We found that top-gate devices are influenced by higher deep acceptor-like states under positive gate bias-temperature stress, whereas the bottom-gate devices suffer reliability degradation under negative gate bias-temperature stress due to the decrease in oxygen content at the bottom interface.

Effect of interfacial excess oxygen on positive-bias temperature stress instability of self-aligned coplanar InGaZnO thin-film transistors

We investigated the impact of excess oxygen on positive bias temperature stress (PBTS) instability of self-aligned coplanar amorphous InGaZnO thin-film transistors. We focus on the interface region which is compositionally differentiated from the bulk material on each side. The threshold voltage shift under PBTS is proportional to the extracted density of interface trap states that act as electron traps. The density of interface trap states is extracted from capacitance-voltage measurements with monochromatic light of varying wavelengths. We introduce a figure-of-merit that quantifies the amount of excess oxygen relative to the metal cation composition in the interface region. Minimization of interfacial excess oxygen from 112.4% to 101.2% reduces the density of interface trap states by a factor of 2.77, resulting in improvement of PBTS instability from a threshold voltage shift value of 4.42 V to 0.35 V.

P‐20: Highly Stable Amorphous Indium Gallium Zinc Oxide Thin‐Film Transistors with N2O Plasma Treatment

Amorphous InGaZnO4 (a-IGZO) thin film transistors (TFTs) are promising devices in backplane technology. Since a-IGZO TFTs are very sensitive to the fabrication processes, they need stable process to keep their initial deposition properties. Herein we improved the stability of a-IGZO by applying N2O plasma. The stability characteristic of a-IGZO TFT was improved with N2O plasma. Vth shift was 1.5V for 10,000s under NBTS with illumination which was the best result in the world.

P-18: Highly Stable a-Si TFT Gate Driver with Simple Logic Circuit

A novel integrated gate driver with a simple logic circuit (SLC) using 5 a-Si TFTs has been developed. The noise voltage owing to clock coupling is eliminated effectively with an overlapped clock controlled transistor. The SLC gate driver, successfully integrated in 14.1-in. XGA TFT-LCDs, shows marked stability despite the extremely simple structure.

Reliability of Crystalline Indium–Gallium–Zinc-Oxide Thin-Film Transistors Under Bias Stress With Light Illumination

We investigate the effect of crystalline indium-gallium-zinc-oxide (c-IGZO) thin films on device performance, and evaluate the device reliability of c-IGZO under positive/negative bias stress with/without illumination. The crystal structure of deposited-IGZO thin film is controlled by annealing temperatures, and the transition from an amorphous to a crystalline structure is observed at above 800 °C. Even though the c-IGZO thin-film transistors (TFTs) exhibit lower carrier mobility, compared with amorphous IGZO (a-IGZO) TFTs, the remarkable improvement of the device reliability for the c-IGZO TFTs is observed especially under the bias stress with illumination. This comes from lower defect density compared with the a-IGZO film.

Improvement in Field-Effect Mobility of Indium Zinc Oxide Transistor by Titanium Metal Reaction Method

This paper examined the effects of postdeposition annealing on the electrical properties of titanium-capped (TC) indium-zinc oxide (IZO) films and their IZO thin-film transistors. The TC IZO transistor oxidized at the temperature of 300 °C exhibited a high field-effect mobility of 61.0 cm2/Vs, low subthreshold gate swing of 110 mV/decade, Vth of -0.4 V, and high ION/OFF ratio of 2.3 × 108. In addition, the positive gate bias stress-induced stability of the TC IZO transistor was better than that of the control device without metal capping treatment. This was attributed to the scavenging effect of the loosely bonded oxygen species in the IZO semiconductor by titanium thermal oxidation.

17.4L: LateNews Paper: Contact Resistance and Process Integration Effects on HighPerformance Oxide TFTs with SolutionDeposited Semiconductor and Gate Dielectric Layers

Highperformance TFTs with solutiondeposited amorphous oxide semiconductor and gate dielectric layers are fabricated at ≤ 350 °C. The initial performance and stability of these TFTs are investigated with respect to device structure and source/drain materials. Topcontact TFTs exhibit better electrical performance and reliability than bottomcontact devices. Representative topcontact device mobility is 1.90 cm2/Vs with an ontooff drain current ratio of 7.0 × 108.

Electromechanical properties of amorphous indium–gallium–zinc-oxide transistors structured with an island configuration on plastic

A comparative study of the electromechanical properties was carried out on a low-temperature-processed amorphous indium–gallium–zinc-oxide thin-film transistor, particularly with regard to the structural design of the device under the stress accumulation of an outward bending surface. Shown herein is the reliable electromechanical integrity of island-structured devices against the mechanical strain at bending radii of mm order. The onset of crack strain also closely corresponded to the electrical failure of the stressed device. These results revealed that the island configuration on the bending surface effectively suppresses the stress accumulation on sheets composed of inorganic stacked layers in a uniaxial direction.

P‐3: Scaling of a‐Si TFT Gate Drivers

The characteristic feature of an optimum design of a-Si gate driver circuits and its scaling properties are presented. The delay time of the output pulse of gate driver circuits with different layout characteristics was analyzed by a distributed-load modeling. The effect of TFT properties, clock phase and the output load on the optimum condition is given. Finally, scaling has been found to give apparent power law dependence on the circuit area, signifying higher performance of the circuits with smaller area.