Yong Ho Jang

A Depletion-Mode a-IGZO TFT Shift Register With a Single Low-Voltage-Level Power Signal

We proposed and fabricated a new depletion-mode amorphous indium-gallium-zinc-oxide thin-film-transistor (a-IGZO TFT) shift register. Although only one low-voltage-level power signal (VGL) rather than widely used two ones was employed, the depletion-mode a-IGZO TFTs in the proposed shift register were turned off completely due to a series-connected two-transistor structure. The proposed shift register exhibited successfully a high-voltage output pulse. The power consumption of the shift register with ten stages is 1.67 mW at the high-voltage-level power signal of 20 V, the VGL of -5 V, and the clock frequency of 13.9 kHz.

Highly Reliable Depletion-Mode a-IGZO TFT Gate Driver Circuits for High-Frequency Display Applications Under Light Illumination

We proposed and fabricated a depletion-mode amorphous indium-gallium-zinc-oxide thin-film transistor gate driver without any additional signals. The proposed gate driver successfully exhibited a high-voltage output pulse without distortion at a clock frequency of 100 kHz, which is enough to drive a high-frequency panel with a frame rate of ~360 Hz and a resolution of full high definition. The experimental and simulation results showed that the gate driver would be highly reliable under light illumination. Also, the output waveform of the gate driver was not distorted after 240-h driving under 450-nm illumination with an intensity of 1 mW/ cm2 at 60°C.

A Novel Level Shifter Employing IGZO TFT

A new level shifter employing indium-gallium-zinc-oxide thin-film transistor (IGZO TFT) for a display panel was proposed and successfully fabricated. Two clock signals with 180° out of phase and a discharging TFT were employed to obtain a full-swing output. The IGZO level shifter has successfully exhibited a wide swing output from VDD to VSS without any additional power sources and input signals. The power consumption is 0.30 mW at a clock frequency of 12.5 kHz. The proposed level shifter with a depletion-mode device would be an important building block for an oxide TFT display.

P-18: Highly Stable a-Si TFT Gate Driver with Simple Logic Circuit

A novel integrated gate driver with a simple logic circuit (SLC) using 5 a-Si TFTs has been developed. The noise voltage owing to clock coupling is eliminated effectively with an overlapped clock controlled transistor. The SLC gate driver, successfully integrated in 14.1-in. XGA TFT-LCDs, shows marked stability despite the extremely simple structure.

P‐3: Scaling of a‐Si TFT Gate Drivers

The characteristic feature of an optimum design of a-Si gate driver circuits and its scaling properties are presented. The delay time of the output pulse of gate driver circuits with different layout characteristics was analyzed by a distributed-load modeling. The effect of TFT properties, clock phase and the output load on the optimum condition is given. Finally, scaling has been found to give apparent power law dependence on the circuit area, signifying higher performance of the circuits with smaller area.

P-27: A Novel IGZO TFT Shift Register with Node-Shared Structure

We propose and design a new depletion-mode In-Ga-Zn-O thin film transistors shift register by employing node-shared structure. The proposed shift register requires 14 TFTs for 2 stages, while the previous shift registers were consisted of more than 20 TFTs for 2 stages. The SPICE simulation results have showed that the proposed shift register has successfully generated two output pulses in one stage.