Bipul C. Paul

Impact of a Process Variation on Nanowire and Nanotube Device Performance

In this paper, we present an in-depth analysis of the nanowire and nanotube device performance under process variability. Although every process parameter variation drastically affects the conventional MOSFET performance, we found that nanowire/nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and geometric properties. It is observed that a two-input nand gate with nanowire or nanotube FETs shows a more than four times less performance variation than its bulk MOSFET counterpart and about two times less than FinFET devices at the 45 and 32 nm technologies, respectively. In other words, nanowire/nanotube FETs will have a larger margin for process parameter variations than bulk and FinFET devices for an allowable performance variation limit. While it is evident that process variations are going to be a major limiting factor for conventional MOSFET devices in future generations, this analysis is expected to further encourage nanowire and nanotube research for high-performance circuit applications.

Optimized Circuit Failure Prediction for Aging: Practicality and Promise

Circuit failure prediction is used to predict occurrences of circuit failures, during system operation, before errors appear in system data and states. This technique is applicable for overcoming major scaled-CMOS reliability challenges posed by aging mechanisms such as Negative-Bias-Temperature-Instability (NBTI). This is possible because of the gradual nature of degradation associated with such aging mechanisms. Circuit failure prediction uses special on-chip circuits called aging sensors. In this paper, we experimentally demonstrate correct functionality and practicality of two flavors of flip-flop designs with built-in aging sensors using 90 nm test chips. We also present an aging-aware timing analysis technique to strategically place such flip-flops with built-in aging sensors at selective locations inside a chip for effective circuit failure prediction. This aging-aware timing analysis approach also minimizes the chip-level area impact of such aging sensors. Results from two 90 nm designs demonstrate the practicality and effectiveness of optimized circuit failure prediction with overall chip-level area impact of 2.5% and 0.6%.

Modeling and analysis of circuit performance of ballistic CNFET

With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this paper, we propose a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit

Solution-processed flexible organic transistors showing very-low subthreshold slope with a bilayer polymeric dielectric on plastic

We demonstrate low-voltage, solution-processed organic transistors on rough plastic substrates with a carrier mobility over 0.2 cm2/V s, a turn-on voltage of near 0 V, and a record low subthreshold slope of ∼80 mV/decade in ambient conditions. These exceptional characteristics are attributed to (1) a device stacking architecture with a conducting polymeric gate and a double layered dielectric composed of low-temperature cross-linked poly(4-vinylphenol), (2) a low interface trap density achieved by modifying the dielectric surface with a phenyl-terminated self-assembled monolayer from 4-phenylbutyltrichlorosilane, and (3) controlled crystallization of a small-molecule organic semiconductor film with favorable charge transport microstructure and a low bulk trap density as deposited by an optimized solution-shearing process. The device performance under different operating voltages was also examined and discussed.

An Analytical Compact Circuit Model for Nanowire FET

In this paper, we propose a quasi-analytical device model of nanowire FET (NWFET) for both ballistic and drift-diffusion current transport, which can be used in any conventional circuit simulator like SPICE. The closed form expressions for current-voltage (I-V) and capacitance-voltage characteristics are obtained by analytically solving device equations with appropriate approximations. The developed model was further verified with the measured I-V characteristics of an NWFET device. Results show a close match of the model with measured data.

Impact of geometry-dependent parasitic capacitances on the performance of CNFET circuits

Intrinsic carbon-nanotube field-effect transistors (CNFETs) have been shown to have superior performance over silicon transistors. In this letter, we provide an insight how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device (gate) width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit.

Fermi level depinning at metal-organic semiconductor interface for low-resistance Ohmic contacts

This paper presents the direct evidence and successful demonstration of Fermi-level depinning at metal-organic semiconductor (M/O) interfaces by inserting an ultrathin interfacial Si3N4 insulator in between. The contact behavior is tuned from rectifying to quasi-Ohmic and to tunneling by varying the Si3N4 thickness within 0–6 nm. Detailed physical mechanisms of Fermi-level pinning/depinning responsible for the M/O contact behavior are clarified based on a proposed lumped-dipole model. Experimental results are in good agreement with the theory and model. This work represents a significant step toward the fundamental understanding of M/O interface properties and technological advancement of achieving low-resistance Ohmic contacts for organic electronic device (e.g. thin-film transistor) applications.

Prospect of ballistic CNFET in high performance applications: Modeling and analysis

With the advent of carbon nanotube technology, evaluating circuit and system performance using these devices is becoming extremely important. In this article, we present a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. This simple quasi-analytical model is effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. We also provide insight into how the parasitic fringe capacitance in state-of-the-art CNFET geometries impacts the overall performance of CNFET circuits. We show that unless the device width can be significantly reduced, the effective gate capacitance of CNFET will be strongly dominated by the parasitic fringe capacitances, and the superior performance of intrinsic CNFET over silicon MOSFET cannot be achieved in circuit. We further show that unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry.

The Prospect and Challenges of CNFET Based Circuits: A Physical Insight

Evaluating circuit and system performance using carbon nanotube transistors (CNFET) is important to predict the prospect of this technology. For this purpose, this chapter presents a quasi-analytical device model for intrinsic ballistic CNFET, which can be used in any conventional circuit simulator like SPICE. The simple quasi-analytical model is seen to be effective in a wide variety of CNFET structures as well as for a wide range of operating conditions in the digital circuit application domain. An estimation of the parasitic fringe capacitance in state-of-the-art CNFET geometries is also provided which impacts the overall performance of CNFET circuits. It is observed that the device width should be significantly reduced in order to achieve the superior performance of intrinsic CNFET over silicon MOSFET in circuits and systems. However, unlike conventional MOSFET, nanotube FETs are significantly less sensitive to many process parameter variations due to their inherent device structures and cylindrical gate geometry. This unique advantage can be effectively utilized in VLSI design to achieve better system performance under variations.