Bo-Han Hwang

A new single-inductor quadratic buck converter using average-current-mode control without slope-compensation

A new single-inductor quadratic buck converter using average-current-mode control without slope-compensation is proposed in this paper. The average-current-mode technology minimizes several power-management problems, such as efficiency, EMI, size, transient response, design complexity, and cost. In DC/DC conversion applications that require a wide range of input and/or output voltages, conventional PWM buck converter topologies always operate at exceptionally low duty ratios, which limit the operation to the lower switching frequencies due to minimum ON-time of the transistor switch. The DC voltage conversion ratio of the proposed converter has a quadratic dependence on duty cycle, producing an extensive step-down; therefore, the high conversion ratio is achieved. This scheme employs an inner loop for current gain and an outer loop for PID-controller. The proposed buck converter only uses an inductor, two capacitors and single control circuit to achieve quadratic conversion ratio, therefore, an inductor and a control circuit is reduced. The advantages of the proposed quadratic buck converter are fast transient response, no use for slope-compensation, high-conversion-ratio, and an inductor reduction. The prototype of the proposed quadratic buck converter has been fabricated with TSMC 0.35µm 2P4M CMOS processes. The total chip area is 1.917 × 2.334 mm2.

A 0.35μm CMOS sub-1V low-quiescent-current low-dropout regulator

A sub-1 V CMOS low-dropout (LDO) voltage regulator with 103 nA low-quiescent current is presented in this paper. The proposed LDO uses a digital error amplifier that can make the quiescent current lower than other LDOs with the traditional error amplifier. Besides, the LDO can be stable even without the output capacitor. With a 0.9 V power supply, the output voltage is designed as 0.5 V. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The prototype of the LDO is fabricated with TSMC 0.35 mum CMOS processes. The active area without pads is only 240 mum times 400 mum.

A sub-1V voltage-mode DC-DC buck converter using PWM control technique

A sub-1V CMOS DC-DC buck converter with 90% efficiency is presented in this paper. The proposed buck converter uses a digital error amplifier that can make the input voltage lower than other conventional buck converters. The buck converter uses voltage-mode control with pulse width modulation (PWM) techniques. The ramp generator of buck converter uses a Schmitt trigger circuit to replace the bias circuit and comparator. The scheme can reduce the power consumption and improving the power efficiency. The buck converter has been implemented with a 0.18-µm CMOS process. The buck converter is designed and the operating frequency is at 1MHz with the inductor of 4.7-uH and the output capacitor of 47-uF to reduce component size and switching loss. Experimental results prove that the converter can be directly powered with 1-V input voltage and output 0.5-V voltage at 500-mA output current.

A new fast-response buck converter using accelerated pulse-width-modulation techniques

SUMMARY A new fast-response buck converter using accelerated pulse-width-modulation techniques is proposed in this article. The benefits of the accelerated pulse-width-modulation technique is fast-transient response, simple-compensation design, and no requirement for slope compensation; furthermore, some power management problems are minimized, such as EMI (Electro Magnetic Interference), size, design complexity, and cost. The traditional voltage-mode speed is slower with the transient response, so an accelerated pulse-width-modulation technique is used to solve the problem of slowed transient response in this article. The proposed buck converter has excellent conversion efficiency with a wide load conditions. The proposed buck converter has been fabricated with TSMC 0.35 µm CMOS 2P4M processes, and the total chip area is 1.32 × 1.22 mm2. Maximum output current is 300 mA when the output voltage equals 1.8 V. When the supply voltage is 3.6 V, the output voltage can be 1–2.6 V. Maximum transient response is less than 5 µs. The simulation and experimental results are presented in this article. Copyright

A dual-loop shunt regulator using current-sensing feedback techniques

The dual-loop shunt regulator using current-sensing feedback techniques is proposed in this paper. This architecture adopts a voltage and current loops to increase the transient response of the proposed shunt regulator. The maximum output current of the proposed shunt regulator is 180mA at a 1.8V output. Moreover the architecture of the proposed shunt regulator can suppress the stray effect which is from power supply. The prototype of the proposed shunt regulator is fabricated by the Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.35-@mm CMOS 2P4M process. The active area is only 579x355@mm^2.

A low-voltage positive buck-boost converter using average-current-controlled techniques

A low-voltage positive buck-boost converter using average-current-controlled techniques is proposed in this paper. The benefit of the average-current-controlled circuit is that it does not need to use slope compensation, furthermore, it can reduce some power management problems such as cost, design complexity, size, and EMI. The advantages of the low-voltage operational amplifier are that it has lower power dynamic consumption and also can operate at low supply voltage. The proposed low-voltage positive buck-boost converter using the active-current-sensing circuit and average-current-controlled circuit techniques can work stably without slope compensation even when the duty cycle is higher than 50%. The proposed design circuit has been fabricated with TSMC 0.35μm CMOS 2P4M processes, the total chip area is 2.46 × 2.47mm2. When the supply voltage is 1.5V, the output voltage range is between 0.8V~3.3V.

A low-voltage low-noise DC-DC flyback converter with delta-sigma modulation

Comparing with buck-boost converter, flyback converter has positive output voltage in switching mode converters, therefore, flyback converter is easier to supply voltage for the rear-end application circuit. The delta-sigma modulator takes important advantage of the noise-shaping and oversampling properties to eliminate the spike in DC-DC flyback converter. Also, comparing with pulse width modulation (PWM), the proposed two-order delta-sigma (ΔΣ) modulator has strong ability of improving the noise rejection in switch-mode converters. It supplies more steady energy to sensitive circuits such as audio amplifier or power amplifier. Because of low-voltage design, the inverter-based operational amplifier is proposed in this work, which can keep operational amplifier good performance. The input voltage of the proposed circuit is 1.5V, and the range of output voltage is from 1V to 3.3V. The chip area is 2.24 × 2.24 mm2.