Bo Pu

Electrical Parameter Extraction of High Performance Package Using PEEC Method

This paper proposes a novel electrical characterization approach for a high-performance package system using an improved Partial Element Equivalent Circuit (PEEC). As the effect of interconnects becomes a pivotal factor for the performance of high-speed electronic systems, there is a great demand for an accurate equivalent model for interconnects. In particular, an equivalent model of interconnects is established in this paper for the Fine-Pitch Ball Grid Array (FBGA) package using the improved PEEC method. Based on the equivalent model, electrical characteristics are analyzed; furthermore, these are verified through the measurement results of a Vector Network Analyzer (VNA).

Modeling and Prediction of Electromagnetic Immunity for Integrated Circuits

An equivalent model has been developed to estimate the electromagnetic immunity for integrated circuits under a complex electromagnetic environment. The complete model is based on the characteristics of the equipment and physical configuration of the device under test (DUT) and describes the measurement setup as well as the target integrated circuits under test, the corresponding package, and a specially designed printed circuit board. The advantage of the proposed model is that it can be applied to a SPICE-like simulator and the immunity of the integrated circuits can be easily achieved without costly and time-consuming measurements. After simulation, measurements were performed to verify the accuracy of the equivalent model for immunity prediction. The improvement of measurement accuracy due to the added effect of a bi-directional coupler in the test setup is also addressed.

Modeling and Parameter Extraction of Coplanar Symmetrical Meander Lines

In this paper, a coplanar symmetrical meander line structure is presented, and an equivalent circuit model is proposed to allow estimation of its electrical characteristics based on numerical modeling. The parasitic couplings in the proposed structure are considerably different from those of a simple meander line with a ground structure below it. Analysis and derivation of inductive and capacitive couplings and of resistance in the effective frequency band are addressed in detail, and the effects of geometrical parameters on the electrical characteristics are also demonstrated. The validity of the proposed equivalent circuit model is verified by both commercial electromagnetic simulator and measurement of the scattering parameters in the frequency domain, as well as of the reflected and transmitted waveforms in the time domain. Because the proposed model is easily coded, and takes little time to compute the parameters, it is very useful in the design of inductance and capacitance in circuits on substrate, which can be used for the design of time-delay elements and stop band filters in power delivery lines.

Electromagnetic susceptibility analysis of ICs using DPI method with consideration of PDN

This paper predicts electromagnetic susceptibility (EMS) of integrated circuits (ICs) with novel consideration of complex power distribution network (PDN). For accurate simulation performance, the set-up model is derived in detail, especially the PDN. PDN model is extracted from the physical configuration and also in view of the function of system to express the ground bounce exactly since it is a pivot factor in DPI test for EMS. After measurement, comparison with simulation result is applied to validate the proposed model and estimate the electromagnetic susceptibility of ICs.

Estimation of Transferred Power from a Noise Source to an IC with Forwarded Power Characteristics

This paper proposes an accurate approach for predicting transferred power from a noise source to integrated circuits based on the characteristics of the power transfer network. A power delivery trace on a package and a printed circuit board are designed to transmit power from an external source to integrated circuits. The power is demonstrated between an injection terminal on the edge of the printed circuit board and integrated circuits, and the power transfer function of the power distribution network is derived. A two-tier calibration is applied to the test, and scattering parameters of the network are measured for the calculation of the power transfer function. After testing to obtain the indispensable parameters, the real received and tolerable power of the integrated circuits can be easily achieved. Our proposed estimation method is an enhancement of the existing the International Electrotechnical Commission standard for precise prediction of the electromagnetic immunity of integrated circuits.

A De-Embedding Technique of a Three-Port Network with Two Ports Coupled

A de-embedding method for multiport networks, especially for coupled odd interconnection lines, is presented in this paper. This method does not require a conversion from S-parameters to T-parameters, which is widely used in the de-embedding technique of multiport networks based on cascaded simple two-port relations, whereas here, we apply an operation to the S-matrix to generate all the uncoupled and coupled coefficients. The derivation of the method is based on the relations of incident and reflected waves between the input of the entire network and the input of the intrinsic device under test (DUT). The characteristics of the intrinsic DUT are eventually achieved and expressed as a function of the S-parameters of the whole network, which are easily obtained. The derived coefficients constitute ABCD-parameters for a convenient implementation of the method into cascaded multiport networks. A validation was performed based on a spice-like circuit simulator, and this verified the proposed method for both uncoupled and coupled cases.

Prediction of Impedance Characteristics of Multi-Layer Ceramic Capacitor Based on Coupled Transmission Line Theory

전자 산업에서의 소형화와 디지털화에 따라 적층 세라믹 커패시터(Multi-Layer Ceramic Capacitors: MLCC) 또한 DC Blocking, 디커플링, 필터링 등의 기능이 이에 부응하여 그 수요가 꾸준히 증가해왔다. 이에 따라 MLCC의 등가회로를 모델링하는 기법이 많이 연구되었는데, 지금까지의 연구를 살펴보면 대부분이 소자의 주파수 특성을 측정한 후, 그 결과 를 바탕으로 소자를 모델링하므로 제작 과정과 측정 과정에서 물질적, 시간적 손실을 수반한다. 이를 해결하기 위한 방 법으로 본 논문에서는 구조 정보와 물질 정보로부터 설계단계에서 MLCC의 임피던스 특성을 예측할 수 있는 모델링 방법을 제시한다. 미분 방정식으로 표현되는 결합 전송선로 방정식으로부터 임의의 N개 층을 가지는 다층 평판 커패시 터(N-Layer Capacitor)의 임피던스를 구조 정보와 물질 정보의 수식으로 표현할 수 있음을 보였다. 이렇게 정의된 임피던 스 수식으로부터 임의의 구조 정보와 물질 정보를 가지는 MLCC의 임피던스를 예측하였으며, EM 시뮬레이션 결과와 비교하였다. 그 결과, 제시한 임피던스 예측 모델링 결과와 측정 결과가 잘 일치하였고, EM 시뮬레이션보다 훨씬 빠르게 예측 결과를 얻을 수 있음을 보였다.

Package design methodology in consideration with signal integrity, power integrity and electromagnetic immunity

A design concept and methodology for package with consideration on signal integrity, power integrity and electromagnetic immunity is proposed in this paper. Each part of the package such as bonding wire, via or bump has a significant influence on the performance of entire chip-package-board system, and these effects to signal, power integrity prosperities are discussed based on the numerical analysis method and SPICE-like simulator. Furthermore, a novel design for filter in package is proposed for enhancing immunity of integrated circuits. Finally, the methodology for design optimization can be achieved based on the analysis results.

Coordinationof the diode and capacitor in the Tx line for the protection of the chipsetfrom EOS

This paper proposes a PCB design method of highspeed signal interface that is robust against electrical overstress (EOS). Surge and electrostatic discharge (ESD) waveforms as defined in the International Electro-technical Commission (IEC)61000-4 standard were used for EOS input waveforms from the connector to the printed circuit board (PCB). Signals in the Tx line of the universal serial bus 3.0 (USB3.0) interface were simulated to analyze the role of the diode and capacitor in the interface circuit, and it was found that the proposed capacitor and diode coordination shows the best combination of schematics for the prevention of EOS. Experiments with an interface circuit in a laptop computer were also performed and the results show that the effectiveness of proposed design is valid.

Design and Crosstalk Analysis of MEMS Probe Connector System

In this paper, we propose a design method that the crosstalk of probe connector pins satisfy the limitation of -30 dB. The parameters(inductance and capacitance) were extracted in the grid-structured probe connector pin system, and it is shown that the new parameters are easily calculated with increasing ground pin numbers using the previously calculated parameters. In addition, the crosstalk reduction algorithm by employing more grounds around the signal pin has been suggested, and it is confirmed that the suggested method is quite effective especially for the reduction of inductive couplings. Finally, we suggested the correlation between the pitch and the length of the pins to satisfy the crosstalk limitation of -30 dB with the given number of ground pins, which will be quite useful when design a probe connector pin system.