SoYoung Kim

On the accuracy of return path assumption for loop inductance extraction for 0.1 /spl mu/m technology and beyond

The most common assumption for chip-level inductance extraction is to restrict the current return path to the closest power or ground lines. This paper shows that this assumption is not necessarily valid for technologies beyond 0.1 /spl mu/m. The actual inductance can exceed twice the value that is extracted from the model considering only the nearest current return paths. Analytical formulae to predict the worst case self inductance are proposed to deal with the errors that result from this assumption. These equations can be used as metrics to decide the size of inductance extraction window for future CAD tools.

Closed-Form RC and RLC Delay Models Considering Input Rise Time

The Elmore delay model is the most popular and efficient delay model used for analytical delay estimation. Closed-form delay formulas are useful for circuit design, timing-driven physical design, synthesis, and optimization. As signal rise time becomes faster and the line resistance becomes smaller from copper technology, the significance of inductance increases. Both RC and RLC delays are a strong function of signal rise time. We propose a novel and efficient delay modeling method based on nondimensionalization to consider finite input rise time as an improvement over the Elmores approach. To further improve the accuracy of the delay model, a new correction method, effective distance correction factor (EDCF), is proposed to consider resistive shielding of downstream capacitance. EDCF can be used to correct the delays for both RC and RLC tree structures. The proposed delay modeling method was applied to a number of nets selected from an integrated circuit (IC) design, and the delay estimation results were compared with HSPICE simulations. The new delay model retains the efficiency and simplicity of the Elmore delay model with significantly improved accuracy.

Modeling of Parasitic Fringing Capacitance in Multifin Trigate FinFETs

In this brief, we analyze the effects of geometrical parameters on the parasitic fringing capacitance of sub 22-nm multifin FinFETs. An analytical model is proposed to compute the fringing capacitance using a conformal mapping technique. To minimize the number of model fitting parameters, nondimensionalization technique is used. The proposed model for gate to source/drain fringing capacitance considers the fin number, whether the fin location is at the edge of the gate, and the source/drain pad that connects the fins. The accuracy of this model is verified with a 2- and 3-D field solver, Raphael.

Power Integrity and Shielding Effectiveness Modeling of Grid Structured Interconnects on PCBs

In this paper, we investigate the power integrity of grid structures for power and ground distribution on printed circuit board (PCB). We propose the 2D transmission line method (TLM)-based model for efficient frequency-dependent impedance characterization and PCB-package-integrated circuit (IC) co-simulation. The model includes an equivalent circuit model of fringing capacitance and probing ports. The accuracy of the proposed grid model is verified with test structure measurements and 3D electromagnetic (EM) simulations. If the grid structures replace the plane structures in PCBs, they should provide effective shielding of the electromagnetic interference in mobile systems. An analytical model to predict the shielding effectiveness (SE) of the grid structures is proposed and verified with EM simulations.

A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-S2 Application

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVBS2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ,m CMOS process with a die area of 0.12 mm². The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

Measurement of Multi-Port S-Parameters using Four-Port Network Analyzer

An efficient measurement methodology is proposed to construct the scattering parameters of a multi-port device using a four-port vector network analyzer (VNA) without the external un-terminated ports. By using the four-port VNA, the reflected waves from the un-terminated ports could be minimized. The proposed method significantly enhances the accuracy of the S-parameters with less number of measurements compared to the results of classical renormalization technique which uses twoport VNA. The proposed method is validated from the measured data with the coupled 8-port micro-strip lines.

An optimization of composition ratio among triple-filled atoms in In 0.3-x-y Ba x Ce y Co 4 Sb 12 system

Bulk nanostructured materials are important as energy materials. Among thermoelectric materials, the skutterudite system of CoSb3 is a representative material of bulk nanostructured materials. Filling a skutterudite structure with atoms that have different localized frequencies (also known as triple filling) was reported to be effective for lowering thermal conductivity. Among studies representing superior power factors, In-filled skutterudite systems showed higher Seebeck coefficients. This study sought to optimize the composition ratio among the triple-filled atoms in an In0.3-x-yBaxCeyCo4Sb12 system. The composition dependence of the thermoelectric properties was investigated for specimens with different ratios among the three kinds of filler atoms in the In0.3-x-yBaxCeyCo4Sb12 system. In addition, the process variables were carefully optimized for filled skutterudite systems to obtain a maximum ZT value.

A three-step power-gating turn-on technique for controlling ground bounce noise

To suppress the ground bounce noise with a minimal wake-up time penalty, a three-step turn-on strategy and its corresponding power-gating structure are proposed. During the circuits meta-stable region of operation, specifically, the amount of current flowing through the sleep transistors is precisely controlled while the virtual or circuit power supply is quickly boosted when the internal nodes of the circuit are stable. In 65 nm CMOS technology, simulation results demonstrate that our technique reduces the peak amplitude of the ground bouncing noise by up to 94% as compared to the conventional abrupt turn-on technique.

On-chip interconnect inductance - friend or foe

Inductance associated with on-chip wires can no longer be ignored as chip operation frequencies increase into GHz regime. Because the magnetic field propagates a very long range, the extraction of wire inductance is not just dependent on the immediate neighboring environment. This paper discusses the various difficulties of extracting inductance of randomly placed wires in a typical chip environment. With dedicated return path, the wire inductance can be controlled and benefit the design of high-speed circuits. Specific examples are illustrated.

Immunity Test for Semiconductor Integrated Circuits Considering Power Transfer Efficiency of the Bulk Current Injection Method

The bulk current injection (BCI) and direct power injection (DPI) method have been established as the standards for the electromagnetic susceptibility (EMS) test. Because the BCI test uses a probe to inject magnetically coupled electromagnetic (EM) noise, there is a significant difference between the power supplied by the radio frequency (RF) generator and that transferred to the integrated circuit (IC). Thus, the immunity estimated by the forward power cannot show the susceptibility of the IC itself. This paper derives the real injected power at the failure point of the IC using the power transfer efficiency of the BCI method. We propose and mathematically derive the power transfer efficiency based on equivalent circuit models representing the BCI test setup. The BCI test is performed on I/O buffers with and without decoupling capacitors, and their immunities are evaluated based on the traditional forward power and the real injected power proposed in this work. The real injected power shows the actual noise power level that the IC can tolerate. Using the real injected power as an indicator for the EMS test, we show that the on-chip decoupling capacitor enhances the EM noise immunity.