Bo Yi

A 300-V Ultra-Low-Specific On-Resistance High-Side p-LDMOS With Auto-Biased n-LDMOS for SPIC

In this paper, a high-side p-channel LDMOS (pLDMOS) with an auto-biased n-channel LDMOS (n-LDMOS) based on Triple-RESURF technology is proposed. The p-LDMOS utilizes both carriers to conduct the on-state current; therefore, the specific on-resistance (Ron,sp) can be much reduced because of much higher electron mobility. The simulation result shows that the proposed 300-V p-LDMOS obtains a Ron,sp of 16.97 mΩ/cm2, which is about 65% reduced compared with the Triple-RESURF silicon limit and is comparable to an optimized n-LDMOS (BV = 340 V, Ron,sp = 18 mΩ/cm2). In addition, due to larger current capability, the active area of the proposed p-LDMOS is only about one third of an optimized Triple-RESURF p-LDMOS. The turn-on (tr) and turn-off time (tf) are reduced by 51.2% and 40.0%, compared to the optimized Triple-RESURF p-LDMOS, respectively.

A new super-junction VDMOS realizing fast reverse recovery

In this paper, the authors propose a new Super-Junction VDMOS structure to realize fast reverse recovery of its body diode. In the proposed SJ-VDMOS, the P-pillar of the drift region is surrounded by a thin SiO2 which prevents the injection of electrons from both the drain and the N-pillar region into the P-pillar region. Thus the stored charges are reduced. A diode D0 integrated outside the edge terminal is used to conduct the electrons collected at the interface of the bottom polysilicon/SiO2 generated during the turning-off state of the VDMOS to prevent pre-breakdown. Besides, a Schottky diode in parallel with the body diode is also integrated to further reduce the reverse recovery charges (Qrr). Simulation results show that the proposed SJ-VDMOS obtains the lowest Qrr = 54 nC without any lifetime control which reduces the total switching power loss in an invertor system to about 48 μJ for a 500 V SJ-VDMOS @ I = 1.6 A.