Junji Cheng

A Practical Approach to Enhance Yield of OPTVLD Products

In the prior art of the optimum variation lateral doping (OPTVLD) technique, the dose deviations between designs and products should be tightly controlled to achieve the eligible breakdown voltages (BVs); however, an approach presented in this letter overcomes this shortcoming without any penalty. Its physical explanation is discussed, and the simulations show that, through using this approach, the allowed dose-deviation range is relaxed from about ±1.5% to about ±5%, which can significantly enhance the yield over the existing state of the art. As a result, at an artificial dose-deviation rate of ±5 %, the OPTVLD products with the high yield of 94.4 % are first fabricated in the BiCMOS process, and the measured maximal BV of 1000 V corresponds very well to the ideal value of 1090 V.

New Planar Junction Edge Termination Technique Using OPTVLD With a Buried Layer

A new planar junction edge termination technique, using the optimum variation lateral doping with a buried layer, is proposed and studied. A voltage equal to 100% of the breakdown voltage of a single-sided abrupt parallel-plane junction with the same substrate can be achieved within a smallest area on the surface. The proposed technique can be realized by a process compatible with conventional CMOS or BiCMOS technologies and verified by the results of numerical simulations.

A Low On-State Voltage and Saturation Current TIGBT With Self-Biased pMOS

A novel trench insulated bipolar transistor (TIGBT) is proposed, where a p-layer beneath the trench gate is introduced to form a self-biased pMOS and provide an additional path for the hole current. In the on-state, the drain-to-source voltage of the trench nMOS is clamped, which helps to decrease the saturation current. In the blocking state, the reverse voltage is sustained by the junction of p-layer/n-drift, so that the n-layer sandwiched by the p-base region and the n-drift region can be as heavily doped as possible to reduce the on-state voltage without affecting the breakdown capability. The simulation results show that, in comparison with the conventional one, under the same breakdown voltage, the saturation current and the on-state voltage of the proposed TIGBT are decreased by 47% and 35%, respectively.

A novel low-side structure for OPTVLD-SPIC technologically compatible with BiCMOS

A novel low-side structure based on the optimum variation lateral doping (OPTVLD) technique, which is formed by many inner VDMOS cells combining an outermost LDMOS, is realized in the 0.8μm BiCMOS-compatible technology. With the benefit of the additional vertical cells, it presents a low specific on-resistance with high breakdown voltage, which significantly advances the prior art. Furthermore, since this low-side structure is capable of being integrated with high-side structure and circuits on a single chip, through the low-cost self-isolation (SI) technology, it is very attractive for fabricating the smart power IC (SPIC) better and cheaper.

A versatile low-cost smart power technology platform for applications over broad current and voltage ranges

A versatile low-cost manufacturing technology, which is based on the optimum variation lateral doping technique, is proposed for smart power ICs in this paper. The proposed technology is capable to combine the lateral and vertical high voltage (> 800V) devices on a single chip, which is suitable for applications over broad current ranges. It is fully compatible with BiCMOS process and has been implemented on a standard CMOS line with only 11 masks. Devices with various breakdown voltages, as well as a switched-mode power supply chip, are successfully fabricated on this platform. The measured results are displayed and discussed in detail.