Bob Gleason

Trade-off between Inverse Lithography Mask Complexity and Lithographic Performance

Improvements in resolution of exposure systems have not kept pace with increasing density of semiconductor products. In order to keep shrinking circuits using equipment with the same basic resolution, lithographers have turned to options such as double-patterning, and have moved beyond model-based OPC in the search for optimal mask patterns. Inverse Lithography Technology (ILT) is becoming one of the strong candidates in 32nm and below single patterning, low-k1 lithography regime. It enables computation of optimum mask patterns to minimize deviations of images from their targets not only at nominal but also over a range of process variations, such as dose, defocus, and mask CD errors. When optimizing for a factor, such as process window, more complex mask patterns are often necessary to achieve the desired depth of focus. Complex mask patterns require more shots when written with VSB systems, increasing the component of mask cost associated with writing time. It can also be more difficult to inspect or repair certain types of complex patterns. Inspection and repair may take more time, or require more expensive equipment compared to the case with simpler masks. For these reasons, we desire to determine the simplest mask patterns that meet necessary lithographic manufacturing objectives. Luminescent ILT provides means to constrain complexity of mask solutions, each of which is optimized to meet lithographic objectives within the bounds of the constraints. Results presented here show trade-offs to process window performance with varying degrees of mask complexity. The paper details ILT mask simplification schemes on contact arrays and random logic, comparing process window trade-offs in each case. Ultimately this method enables litho and mask engineers balance lithographic requirements with mask manufacturing complexity and related cost.

Source-Mask co-Optimization (SMO) using Level Set Methods

Masks computed by use of Inverse Lithography Technology (ILT) are being increasingly used in 32nm and below nodes for their significantly better litho performance outperforming model-based OPC [1,2]. This technique poses the design of photomasks as an inverse problem and then solves for the optimal photomask using rigorous mathematical approach [3,4]. One such approach is the level set based method [5] wherein a level set function φ(x,y) is made to represent the contour of the mask. The zero level set φ(x,y)=0 then represents the actual mask at a given instance. The same level-set technique has now been extended to determine the most optimized source φ(p,q) for a given target or mask. Cooptimization of both the source and mask is a natural extension of optimizing the mask alone in ILT. The same cost function, say maximizing DOF, which is used to compute the ILT mask can be used for the source optimization as well. This approach enables accurate and fast computation of the optimized source and mask for given set of patterns and also utilizes running on a distributed computing environment. In this paper, the level set based SMO approach will be first validated on simple contact array patterns and then extended to the optimization of sample 22nm logic contact design patterns, including array, SRAM and random logic. The effect of using different emphasis in defining the cost function will also be studied.

Source mask optimization (SMO) at full chip scale using inverse lithography technology (ILT) based on level set methods

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. For years, source optimization and mask pattern correction have been conducted as two separate RET steps. For source optimization, the source was optimized based on fixed mask patterns; in other words, OPC and SRAFs were not considered during source optimization. Recently, some new approaches to Source Mask Optimization (SMO) have been introduced for the lithography development stage. The next important step would be the extension of SMO, and in particular the mask optimization in SMO, into full chip. In this paper, a computational framework based on Level Set Method is presented that enables simultaneous source and mask optimization (using Inverse Lithography Technology, or ILT), and can extend the SMO from single clip, to multiple clips, all the way to full chip. Memory and logic device results at the 32nm node and below are presented which demonstrate the benefits of this level-set-method-based SMO and its extendibility to full chip designs.

Enhancing fullchip ILT mask synthesis capability for IC manufacturability

It is well known in the industry that the technology nodes from 30nm and below will require model based SRAF / OPC for critical layers to meet production required process windows. Since the seminal paper by Saleh and Sayegh[1][2] thirty years ago, the idea of using inverse methods to solve mask layout problems has been receiving increasing attention as design sizes have been steadily shrinking. ILT in its present form represents an attempt to construct the inverse solution to a constrained problem where the constraints are all possible phenomena which can be simulated, including: DOF, sidelobes, MRC, MEEF, EL, shot-count, and other effects. Given current manufacturing constraints and process window requirements, inverse solutions must use all possible degrees of freedom to synthesize a mask. Various forms of inverse solutions differ greatly with respect to lithographic performance and mask complexity. Factors responsible for their differences include composition of the cost function that is minimized, constraints applied during optimization to ensure MRC compliance and limit complexity, and the data structure used to represent mask patterns. In this paper we describe the level set method to represent mask patterns, which allows the necessary degrees of freedom for required lithographic performance, and show how to derive Manhattan mask patterns from it, which can be manufactured with controllable complexity and limited shot-counts. We will demonstrate how full chip ILT masks can control e-beam write-time to the level comparable to traditional OPC masks, providing a solution with maximized lithographic performance and manageable cost of ownership that is vital to sub-30nm node IC manufacturing.

Source-mask optimization (SMO): from theory to practice

Source Mask Optimization techniques are gaining increasing attention as RET computational lithography techniques in sub-32nm design nodes. However, practical use of this technique requires careful considerations in the use of the obtained pixilated or composite source and mask solutions, along with accurate modeling of mask, resist, and optics, including scanner scalar and vector aberrations as part of the optimization process. We present here a theory-to-practice case of applying ILT-based SMO on 22nm design patterns.

Optimization from design rules, source and mask, to full chip with a single computational lithography framework: level-set-methods-based inverse lithography technology (ILT)

For semiconductor manufacturers moving toward advanced technology nodes -32nm, 22nm and below - lithography presents a great challenge, because it is fundamentally constrained by basic principles of optical physics. Because no major lithography hardware improvements are expected over the next couple years, Computational Lithography has been recognized by the industry as the key technology needed to drive lithographic performance. This implies not only simultaneous co-optimization of all the lithographic enhancement tricks that have been learned over the years, but that they also be pushed to the limit by powerful computational techniques and systems. In this paper a single computational lithography framework for design, mask, and source co-optimization will be explained in non-mathematical language. A number of memory and logic device results at the 32nm node and below are presented to demonstrate the benefits of Level-Set-Method-based ILT in applications covering design rule optimization, SMO, and full-chip correction.

Evaluation of Inverse Lithography Technology for 55nm-node memory device

Model based OPC has been generally used to correct proximity effects down to ~50 nm critical dimensions at k1 values around 0.3. As design rules shrink and k1 drops below 0.3, however; it is very hard to obtain enough process window and acceptable MEEF (Mask Error Enhancement Factor) with conventional model based OPC. Recently, ILT (Inverse Lithography Technology) has been introduced and has demonstrated wider process windows than conventional OPC. The ILT developed by Luminescent uses level-set methods to find the optimal photo mask layout, which maximizes the process window subject to mask manufacturing constraints. We have evaluated performance of ILT for critical dimensions of 55nm, printed under conditions corresponding to k1 ~ 0.28. Results indicated a larger process window and better pattern fidelity than obtained with other methods. In this paper, we present the optimization procedures, model calibration and evaluation results for 55 nm metal and contact layers and discuss the possibilities and the limitations of this new technology.

Exploring the impact of mask making constraints on double patterning design rules

In order to achieve an economical design-to-mask (DTM) development cycle in the low k1 domain, designers, lithographers, and mask makers needed to move away from many sequentially isolated developmental activities onto one collaborative environment managed by a computational lithography platform that integrates their respective ecosystems. 1,2 A successful development cycle used to be achievable by designers providing designs to lithographers, who then provided RET/OPC solutions to realize designs, but once k1 fell below a certain level, the lithographers could not provide solutions to realize some critical designs, which then required feedback to designers for further redesigns requiring further lithographic evaluation cycles. So collaboration and automations between lithographers and designers became necessary to reduce feedback loops and development cycle time. RET and design solutions also were impacted by mask making, and so mask makers feedback on MRC and other constraints needed to be integrated for all three groups to achieve an economical DTM. As many lithographers attempted to print sub-80 nm pitches with 193 nm wavelength, it became necessary to use double patterning to achieve feature resolution. With the effective pitch doubling on each split layer, there could be significant increased design rule freedom for certain complex design situations. Using an integrated computational lithographic platform, one could find design space sweet spots that could further achieve optimal lithographic performance. In this paper, the optimization of design rules (DRD) for double pattern designs (~60 nm pitch) was explored with the mask makers perspective. The experiment to be presented started with a 2x nm design set of clips. Each set of clips underwent size/width/space/pitch variations to generate a design space, and then each design space underwent SMO with an inverse lithography technology (ILT) engine using various mask MRCs and manhattan segmentations. The lithographic results were analyzed with respect to MRC and manhattan segmentation to show their impact on design space and mask solutions.

Litho/Design Co-Optimization and Area Scaling for the 22-nm Logic Node

We present a comprehensive study of area scaling for 22nm-logicnode routed metal/via layers as a function of route pitch and patterning strategy in both single-exposure (SE) and doublepatterning (DP) regimes. For each candidate route pitch (8856nm), we determine an optimal illumination scheme and develop layout rules for the metal layers. A perturbative area model is used to approximate the impact of the candidate rule set on area scaling. For the most promising SE case, we apply a novel ‘source/design optimization’ technique to further optimize illumination and rules, wherein we extend the source-mask optimization approach (1) by allowing design rules to vary in the analysis. We demonstrate that the optimal area scaling achievable with DP techniques can be vastly superior to SE, and therefore may justify the associated additional cost per wafer.

Evaluation of lithographic benefits of using ILT techniques for 22nm-node

As increasing complexity of design and scaling continue to push lithographic imaging to its k1 limit, lithographers have been developing computational lithography solutions to extend 193nm immersion lithography to the 22nm technology node. In our paper, we investigate the beneficial source or mask solutions with respect to pattern fidelity and process variation (PV) band performances for 1D through pitch patterns, SRAM and Random Logic Standard Cells. The performances of two different computational lithography solutions, idealized un-constrained ILT mask and manhattanized mask rule constrain (MRC) compliant mask, are compared. Additionally performance benefits for process-window aware hybrid assist feature (AF) are gauged against traditional rule-based AF. The results of this study will demonstrate the lithographic performance contribution that can be obtained from these mask optimization techniques in addition to what source optimization can achieve.